From e3a5d6fc19102969cb1a5359cc436dcba962b68e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 4 Mar 2024 16:19:08 +0100 Subject: [PATCH] phy/pcs_1000basex: Expose timers to ease debug. --- liteeth/phy/pcs_1000basex.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/liteeth/phy/pcs_1000basex.py b/liteeth/phy/pcs_1000basex.py index e2e962c..d750d95 100644 --- a/liteeth/phy/pcs_1000basex.py +++ b/liteeth/phy/pcs_1000basex.py @@ -375,10 +375,9 @@ class PCS(LiteXModule): rx_config_reg_ack = PulseSynchronizer("eth_rx", "eth_tx") self.submodules += rx_config_reg_abi, rx_config_reg_ack - more_ack_timer = ClockDomainsRenamer("eth_tx")(WaitTimer(ceil(more_ack_time*125e6))) + self.more_ack_timer = more_ack_timer = ClockDomainsRenamer("eth_tx")(WaitTimer(ceil(more_ack_time*125e6))) # SGMII: use 1.6ms link_timer - sgmii_ack_timer = ClockDomainsRenamer("eth_tx")(WaitTimer(ceil(1.6e-3*125e6))) - self.submodules += more_ack_timer, sgmii_ack_timer + self.sgmii_ack_timer = sgmii_ack_timer = ClockDomainsRenamer("eth_tx")(WaitTimer(ceil(1.6e-3*125e6))) self.fsm = fsm = ClockDomainsRenamer("eth_tx")(FSM()) # AN_ENABLE