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phy/pcs_1000basex: Expose timers to ease debug.

This commit is contained in:
Florent Kermarrec 2024-03-04 16:19:08 +01:00
parent ab4606c5a1
commit e3a5d6fc19
1 changed files with 2 additions and 3 deletions
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5
liteeth/phy/pcs_1000basex.py
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@ -375,10 +375,9 @@ class PCS(LiteXModule):
rx_config_reg_ack = PulseSynchronizer("eth_rx", "eth_tx") rx_config_reg_ack = PulseSynchronizer("eth_rx", "eth_tx")
self.submodules += rx_config_reg_abi, rx_config_reg_ack self.submodules += rx_config_reg_abi, rx_config_reg_ack
more_ack_timer = ClockDomainsRenamer("eth_tx")(WaitTimer(ceil(more_ack_time*125e6))) self.more_ack_timer = more_ack_timer = ClockDomainsRenamer("eth_tx")(WaitTimer(ceil(more_ack_time*125e6)))
# SGMII: use 1.6ms link_timer # SGMII: use 1.6ms link_timer
sgmii_ack_timer = ClockDomainsRenamer("eth_tx")(WaitTimer(ceil(1.6e-3*125e6))) self.sgmii_ack_timer = sgmii_ack_timer = ClockDomainsRenamer("eth_tx")(WaitTimer(ceil(1.6e-3*125e6)))
self.submodules += more_ack_timer, sgmii_ack_timer
self.fsm = fsm = ClockDomainsRenamer("eth_tx")(FSM()) self.fsm = fsm = ClockDomainsRenamer("eth_tx")(FSM())
# AN_ENABLE # AN_ENABLE