diff --git a/bench/arty.py b/bench/arty.py
index f2fbea1..ad04278 100755
--- a/bench/arty.py
+++ b/bench/arty.py
@@ -11,9 +11,9 @@ import argparse
 
 from migen import *
 from migen.genlib.cdc import MultiReg
-from migen.genlib.misc import WaitTimer
 
 from litex.gen import *
+from litex.gen.genlib.misc import WaitTimer
 
 from litex_boards.platforms import digilent_arty
 from litex_boards.targets.digilent_arty import _CRG
diff --git a/liteeth/core/arp.py b/liteeth/core/arp.py
index 18ccfbc..ba6df9c 100644
--- a/liteeth/core/arp.py
+++ b/liteeth/core/arp.py
@@ -6,7 +6,7 @@
 
 from liteeth.common import *
 
-from migen.genlib.misc import WaitTimer
+from litex.gen.genlib.misc import WaitTimer
 
 from liteeth.packet import Depacketizer, Packetizer
 
diff --git a/liteeth/core/dhcp.py b/liteeth/core/dhcp.py
index 08c2152..0cf4963 100644
--- a/liteeth/core/dhcp.py
+++ b/liteeth/core/dhcp.py
@@ -19,9 +19,9 @@ issue a DHCP request regularly. Limitations is due to 32-bit data-path and parsi
 """
 
 from migen import *
-from migen.genlib.misc import WaitTimer
 
 from litex.gen import *
+from litex.gen.genlib.misc import WaitTimer
 
 from liteeth.common import *
 
diff --git a/liteeth/mac/crc.py b/liteeth/mac/crc.py
index f2e167f..9f3b0eb 100644
--- a/liteeth/mac/crc.py
+++ b/liteeth/mac/crc.py
@@ -15,7 +15,7 @@ from math import ceil
 
 from liteeth.common import *
 
-from migen.genlib.misc import chooser, WaitTimer
+from litex.gen.genlib.misc import chooser, WaitTimer
 
 # MAC CRC Engine -----------------------------------------------------------------------------------
 
diff --git a/liteeth/mac/preamble.py b/liteeth/mac/preamble.py
index 4a04e6f..2ae6484 100644
--- a/liteeth/mac/preamble.py
+++ b/liteeth/mac/preamble.py
@@ -9,7 +9,7 @@
 
 from liteeth.common import *
 
-from migen.genlib.misc import chooser
+from litex.gen.genlib.misc import chooser
 
 # MAC Preamble Inserter ----------------------------------------------------------------------------
 
diff --git a/liteeth/phy/pcs_1000basex.py b/liteeth/phy/pcs_1000basex.py
index af06a77..624077a 100644
--- a/liteeth/phy/pcs_1000basex.py
+++ b/liteeth/phy/pcs_1000basex.py
@@ -8,10 +8,10 @@ from math import ceil
 
 from migen import *
 from migen.genlib.fsm import *
-from migen.genlib.misc import WaitTimer
 from migen.genlib.cdc import PulseSynchronizer, BusSynchronizer
 
 from litex.gen import *
+from litex.gen.genlib.misc import WaitTimer
 
 from litex.soc.interconnect import stream
 from litex.soc.cores.code_8b10b import K, D, Encoder, Decoder