From e5746c8a8125d18eede8c39c4b45560c45a46666 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 15 Oct 2024 09:47:46 +0200 Subject: [PATCH] phy/pcs_1000basex: Add missing RX Align during AUTONEG_WAIT_ABI state and enable/connect it on all PHYs. --- liteeth/phy/a7_1000basex.py | 6 +++--- liteeth/phy/k7_1000basex.py | 6 +++--- liteeth/phy/ku_1000basex.py | 6 +++--- liteeth/phy/pcs_1000basex.py | 3 +++ liteeth/phy/usp_gth_1000basex.py | 6 +++--- liteeth/phy/usp_gty_1000basex.py | 6 +++--- liteeth/phy/v7_1000basex.py | 6 +++--- 7 files changed, 21 insertions(+), 18 deletions(-) diff --git a/liteeth/phy/a7_1000basex.py b/liteeth/phy/a7_1000basex.py index 14d8471..995a388 100644 --- a/liteeth/phy/a7_1000basex.py +++ b/liteeth/phy/a7_1000basex.py @@ -505,9 +505,9 @@ class A7_1000BASEX(LiteXModule): o_RXBYTEISALIGNED = Open(), o_RXBYTEREALIGN = Open(), o_RXCOMMADET = Open(), - i_RXCOMMADETEN = 0, - i_RXMCOMMAALIGNEN = 0, - i_RXPCOMMAALIGNEN = 0, + i_RXCOMMADETEN = 0b1, + i_RXMCOMMAALIGNEN = pcs.align, + i_RXPCOMMAALIGNEN = pcs.align, i_RXSLIDE = 0, # Receive Ports - RX Channel Bonding Ports o_RXCHANBONDSEQ = Open(), diff --git a/liteeth/phy/k7_1000basex.py b/liteeth/phy/k7_1000basex.py index d9e9526..a872c73 100644 --- a/liteeth/phy/k7_1000basex.py +++ b/liteeth/phy/k7_1000basex.py @@ -484,9 +484,9 @@ class K7_1000BASEX(LiteXModule): o_RXBYTEISALIGNED = Open(), o_RXBYTEREALIGN = Open(), o_RXCOMMADET = Open(), - i_RXCOMMADETEN = 1, - i_RXMCOMMAALIGNEN = 1, - i_RXPCOMMAALIGNEN = 1, + i_RXCOMMADETEN = 0b1, + i_RXMCOMMAALIGNEN = pcs.align, + i_RXPCOMMAALIGNEN = pcs.align, # Receive Ports - RX Channel Bonding Ports o_RXCHANBONDSEQ = Open(), diff --git a/liteeth/phy/ku_1000basex.py b/liteeth/phy/ku_1000basex.py index 2552fab..4177a12 100644 --- a/liteeth/phy/ku_1000basex.py +++ b/liteeth/phy/ku_1000basex.py @@ -536,7 +536,7 @@ class KU_1000BASEX(LiteXModule): i_RXCHBONDLEVEL = 0b000, i_RXCHBONDMASTER = 0b0, i_RXCHBONDSLAVE = 0b0, - i_RXCOMMADETEN = 0b0, + i_RXCOMMADETEN = 0b1, i_RXDFEAGCCTRL = 0b01, i_RXDFEAGCHOLD = 0b0, i_RXDFEAGCOVRDEN = 0b0, @@ -593,7 +593,7 @@ class KU_1000BASEX(LiteXModule): i_RXLPMLFKLOVRDEN = 0b0, i_RXLPMOSHOLD = 0b0, i_RXLPMOSOVRDEN = 0b0, - i_RXMCOMMAALIGNEN = 0b0, + i_RXMCOMMAALIGNEN = pcs.align, i_RXMONITORSEL = 0b00, i_RXOOBRESET = 0b0, i_RXOSCALRESET = 0b0, @@ -606,7 +606,7 @@ class KU_1000BASEX(LiteXModule): i_RXOSINTTESTOVRDEN = 0b0, i_RXOSOVRDEN = 0b0, i_RXOUTCLKSEL = 0b101, - i_RXPCOMMAALIGNEN = 0b0, + i_RXPCOMMAALIGNEN = pcs.align, i_RXPCSRESET = 0b0, i_RXPD = 0b00, i_RXPHALIGNEN = 0b0, diff --git a/liteeth/phy/pcs_1000basex.py b/liteeth/phy/pcs_1000basex.py index 2a17532..8892a5e 100644 --- a/liteeth/phy/pcs_1000basex.py +++ b/liteeth/phy/pcs_1000basex.py @@ -297,6 +297,8 @@ class PCS(LiteXModule): self.link_up = Signal() self.restart = Signal() + self.align = Signal() + self.lp_abi = BusSynchronizer(16, "eth_rx", "eth_tx") @@ -387,6 +389,7 @@ class PCS(LiteXModule): ) # ABILITY_DETECT fsm.act("AUTONEG_WAIT_ABI", + self.align.eq(1), self.tx.config_valid.eq(1), If(rx_config_reg_abi.o, NextState("AUTONEG_WAIT_ACK") diff --git a/liteeth/phy/usp_gth_1000basex.py b/liteeth/phy/usp_gth_1000basex.py index 04f253f..09fe8bf 100644 --- a/liteeth/phy/usp_gth_1000basex.py +++ b/liteeth/phy/usp_gth_1000basex.py @@ -612,7 +612,7 @@ class USP_GTH_1000BASEX(LiteXModule): i_RXCHBONDLEVEL = 0b000, i_RXCHBONDMASTER = 0b0, i_RXCHBONDSLAVE = 0b0, - i_RXCOMMADETEN = 0b0, + i_RXCOMMADETEN = 0b1, i_RXDFEAGCCTRL = 0b01, i_RXDFEAGCHOLD = 0b0, i_RXDFEAGCOVRDEN = 0b0, @@ -668,14 +668,14 @@ class USP_GTH_1000BASEX(LiteXModule): i_RXLPMLFKLOVRDEN = 0b0, i_RXLPMOSHOLD = 0b0, i_RXLPMOSOVRDEN = 0b0, - i_RXMCOMMAALIGNEN = 0b0, + i_RXMCOMMAALIGNEN = pcs.align, i_RXMONITORSEL = 0b00, i_RXOOBRESET = 0b0, i_RXOSCALRESET = 0b0, i_RXOSHOLD = 0b0, i_RXOSOVRDEN = 0b0, i_RXOUTCLKSEL = 0b101, - i_RXPCOMMAALIGNEN = 0b0, + i_RXPCOMMAALIGNEN = pcs.align, i_RXPCSRESET = 0b0, i_RXPD = 0b00, i_RXPHALIGNEN = 0b0, diff --git a/liteeth/phy/usp_gty_1000basex.py b/liteeth/phy/usp_gty_1000basex.py index 5e1f3c8..4125fae 100644 --- a/liteeth/phy/usp_gty_1000basex.py +++ b/liteeth/phy/usp_gty_1000basex.py @@ -641,7 +641,7 @@ class USP_GTY_1000BASEX(LiteXModule): i_RXCHBONDSLAVE = 0b0, i_RXCKCALRESET = 0b0, i_RXCKCALSTART = 0b0, - i_RXCOMMADETEN = 0b0, + i_RXCOMMADETEN = 0b1, i_RXDFEAGCHOLD = 0b0, i_RXDFEAGCOVRDEN = 0b0, i_RXDFECFOKFCNUM = 0b0, @@ -704,14 +704,14 @@ class USP_GTY_1000BASEX(LiteXModule): i_RXLPMLFKLOVRDEN = 0b0, i_RXLPMOSHOLD = 0b0, i_RXLPMOSOVRDEN = 0b0, - i_RXMCOMMAALIGNEN = 0b0, + i_RXMCOMMAALIGNEN = pcs.align, i_RXMONITORSEL = 0b00, i_RXOOBRESET = 0b0, i_RXOSCALRESET = 0b0, i_RXOSHOLD = 0b0, i_RXOSOVRDEN = 0b0, i_RXOUTCLKSEL = 0b101, - i_RXPCOMMAALIGNEN = 0b0, + i_RXPCOMMAALIGNEN = pcs.align, i_RXPCSRESET = 0b0, i_RXPD = 0b00, i_RXPHALIGN = 0b0, diff --git a/liteeth/phy/v7_1000basex.py b/liteeth/phy/v7_1000basex.py index 7b899d6..d5bbdf4 100644 --- a/liteeth/phy/v7_1000basex.py +++ b/liteeth/phy/v7_1000basex.py @@ -479,9 +479,9 @@ class V7_1000BASEX(LiteXModule): o_RXBYTEISALIGNED = Open(), o_RXBYTEREALIGN = Open(), o_RXCOMMADET = Open(), - i_RXCOMMADETEN = 1, - i_RXMCOMMAALIGNEN = 1, - i_RXPCOMMAALIGNEN = 1, + i_RXCOMMADETEN = 0b1, + i_RXMCOMMAALIGNEN = pcs.align, + i_RXPCOMMAALIGNEN = pcs.align, # Receive Ports - RX Channel Bonding Ports o_RXCHANBONDSEQ = Open(),