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core/arp: Use signals for alias to simplify debug.

This commit is contained in:
Florent Kermarrec 2023-10-11 09:03:19 +02:00
parent 79600f954a
commit e784bf8fd3
1 changed files with 16 additions and 6 deletions
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22
liteeth/core/arp.py
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@ -187,14 +187,24 @@ class LiteEthARPCache(LiteXModule):
self.specials += mem, mem_wr_port, mem_rd_port self.specials += mem, mem_wr_port, mem_rd_port
# Memory wr_port aliases. # Memory wr_port aliases.
mem_wr_port_valid = mem_wr_port.dat_w[80] mem_wr_port_valid = Signal()
mem_wr_port_ip_address = mem_wr_port.dat_w[0:32] mem_wr_port_ip_address = Signal(32)
mem_wr_port_mac_address = mem_wr_port.dat_w[32:80] mem_wr_port_mac_address = Signal(48)
self.comb += [
mem_wr_port_valid.eq(mem_wr_port.dat_w[80]),
mem_wr_port_ip_address.eq(mem_wr_port.dat_w[0:32]),
mem_wr_port_mac_address.eq(mem_wr_port.dat_w[32:80]),
]
# Memory rd_port aliases. # Memory rd_port aliases.
mem_rd_port_valid = mem_rd_port.dat_r[80] mem_rd_port_valid = Signal()
mem_rd_port_ip_address = mem_rd_port.dat_r[0:32] mem_rd_port_ip_address = Signal(32)
mem_rd_port_mac_address = mem_rd_port.dat_r[32:80] mem_rd_port_mac_address = Signal(48)
self.comb += [
mem_rd_port_valid.eq(mem_rd_port.dat_r[80]),
mem_rd_port_ip_address.eq(mem_rd_port.dat_r[0:32]),
mem_rd_port_mac_address.eq(mem_rd_port.dat_r[32:80]),
]
# Clear Timer to clear table every 1s. # Clear Timer to clear table every 1s.
self.clear_timer = WaitTimer(1e-0*clk_freq) self.clear_timer = WaitTimer(1e-0*clk_freq)