From e794459946f1c5d96b8fb9bb2cc9af2f5ba4dbef Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 1 Oct 2021 18:30:37 +0200 Subject: [PATCH] mac: Move sram dw/sram checks to LiteEthMAC. --- liteeth/mac/__init__.py | 6 +++++- liteeth/mac/sram.py | 5 ----- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/liteeth/mac/__init__.py b/liteeth/mac/__init__.py index 39d85fb..c9f6491 100644 --- a/liteeth/mac/__init__.py +++ b/liteeth/mac/__init__.py @@ -22,7 +22,11 @@ class LiteEthMAC(Module, AutoCSR): timestamp = None, full_memory_we = False, sys_data_path = False): - assert interface in ["crossbar", "wishbone", "hybrid"] + + assert dw%8 == 0 + assert interface in ["crossbar", "wishbone", "hybrid"] + assert endianness in ["big", "little"] + self.submodules.core = LiteEthMACCore(phy, dw, with_preamble_crc, sys_data_path) self.csrs = [] if interface == "crossbar": diff --git a/liteeth/mac/sram.py b/liteeth/mac/sram.py index 42f3add..87b6437 100644 --- a/liteeth/mac/sram.py +++ b/liteeth/mac/sram.py @@ -18,8 +18,6 @@ from litex.soc.interconnect.csr_eventmanager import * class LastBEDecoder(Module): def __init__(self, dw, last_be): - assert dw % 8 == 0, "dw must be evenly divisible by 8!" - bytes = dw // 8 # Decoded needs to be able to represent a count from 0 up to @@ -37,7 +35,6 @@ class LastBEDecoder(Module): class LastBEEncoder(Module): def __init__(self, dw, length_lsb): - assert dw % 8 == 0, "dw must be evenly divisible by 8!" bytes = dw // 8 self.encoded = Signal(bytes) @@ -50,8 +47,6 @@ class LastBEEncoder(Module): class LiteEthMACSRAMWriter(Module, AutoCSR): def __init__(self, dw, depth, nslots=2, endianness="big", timestamp=None): - assert endianness in [ - "big", "little"], "endianness must be either big or litte!" self.sink = sink = stream.Endpoint(eth_phy_description(dw)) self.crc_error = Signal()