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core/udp: Switch to LiteXModule.

This commit is contained in:
Florent Kermarrec 2023-07-10 10:24:56 +02:00
parent f3d08e589b
commit e7ea355959
1 changed files with 22 additions and 19 deletions
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41
liteeth/core/udp.py
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@ -1,14 +1,15 @@
# #
# This file is part of LiteEth. # This file is part of LiteEth.
# #
# Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2015-2023 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
from liteeth.common import * from litex.gen import *
from liteeth.crossbar import LiteEthCrossbar
from litex.soc.interconnect import stream from litex.soc.interconnect import stream
from liteeth.common import *
from liteeth.crossbar import LiteEthCrossbar
from liteeth.packet import Depacketizer, Packetizer from liteeth.packet import Depacketizer, Packetizer
# UDP Crossbar ------------------------------------------------------------------------------------- # UDP Crossbar -------------------------------------------------------------------------------------
@ -48,7 +49,7 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
# --- # ---
# CDC. # CDC.
self.submodules.tx_cdc = tx_cdc = stream.ClockDomainCrossing( self.tx_cdc = tx_cdc = stream.ClockDomainCrossing(
layout = eth_udp_user_description(user_port.dw), layout = eth_udp_user_description(user_port.dw),
cd_from = cd, cd_from = cd,
cd_to ="sys" cd_to ="sys"
@ -56,7 +57,7 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
self.comb += user_port.sink.connect(tx_cdc.sink) self.comb += user_port.sink.connect(tx_cdc.sink)
# Data-Width Conversion. # Data-Width Conversion.
self.submodules.tx_converter = tx_converter = stream.StrideConverter( self.tx_converter = tx_converter = stream.StrideConverter(
description_from = eth_udp_user_description(user_port.dw), description_from = eth_udp_user_description(user_port.dw),
description_to = eth_udp_user_description(self.dw) description_to = eth_udp_user_description(self.dw)
) )
@ -68,14 +69,14 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
# RX # RX
# -- # --
# Data-Width Conversion. # Data-Width Conversion.
self.submodules.rx_converter = rx_converter = stream.StrideConverter( self.rx_converter = rx_converter = stream.StrideConverter(
description_from = eth_udp_user_description(self.dw), description_from = eth_udp_user_description(self.dw),
description_to = eth_udp_user_description(user_port.dw) description_to = eth_udp_user_description(user_port.dw)
) )
self.comb += internal_port.source.connect(rx_converter.sink) self.comb += internal_port.source.connect(rx_converter.sink)
# CDC. # CDC.
self.submodules.rx_cdc = rx_cdc = stream.ClockDomainCrossing( self.rx_cdc = rx_cdc = stream.ClockDomainCrossing(
layout = eth_udp_user_description(user_port.dw), layout = eth_udp_user_description(user_port.dw),
cd_from = "sys", cd_from = "sys",
cd_to = cd cd_to = cd
@ -98,10 +99,11 @@ class LiteEthUDPPacketizer(Packetizer):
Packetizer.__init__(self, Packetizer.__init__(self,
eth_udp_description(dw), eth_udp_description(dw),
eth_ipv4_user_description(dw), eth_ipv4_user_description(dw),
udp_header) udp_header
)
class LiteEthUDPTX(Module): class LiteEthUDPTX(LiteXModule):
def __init__(self, ip_address, dw=8): def __init__(self, ip_address, dw=8):
self.sink = sink = stream.Endpoint(eth_udp_user_description(dw)) self.sink = sink = stream.Endpoint(eth_udp_user_description(dw))
self.source = source = stream.Endpoint(eth_ipv4_user_description(dw)) self.source = source = stream.Endpoint(eth_ipv4_user_description(dw))
@ -109,7 +111,7 @@ class LiteEthUDPTX(Module):
# # # # # #
# Packetizer. # Packetizer.
self.submodules.packetizer = packetizer = LiteEthUDPPacketizer(dw=dw) self.packetizer = packetizer = LiteEthUDPPacketizer(dw=dw)
# Data-Path. # Data-Path.
self.comb += [ self.comb += [
@ -126,7 +128,7 @@ class LiteEthUDPTX(Module):
] ]
# Control-Path (FSM). # Control-Path (FSM).
self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE", fsm.act("IDLE",
If(packetizer.source.valid, If(packetizer.source.valid,
NextState("SEND") NextState("SEND")
@ -151,10 +153,11 @@ class LiteEthUDPDepacketizer(Depacketizer):
Depacketizer.__init__(self, Depacketizer.__init__(self,
eth_ipv4_user_description(dw), eth_ipv4_user_description(dw),
eth_udp_description(dw), eth_udp_description(dw),
udp_header) udp_header
)
class LiteEthUDPRX(Module): class LiteEthUDPRX(LiteXModule):
def __init__(self, ip_address, dw=8): def __init__(self, ip_address, dw=8):
self.sink = sink = stream.Endpoint(eth_ipv4_user_description(dw)) self.sink = sink = stream.Endpoint(eth_ipv4_user_description(dw))
self.source = source = stream.Endpoint(eth_udp_user_description(dw)) self.source = source = stream.Endpoint(eth_udp_user_description(dw))
@ -162,7 +165,7 @@ class LiteEthUDPRX(Module):
# # # # # #
# Depacketizer. # Depacketizer.
self.submodules.depacketizer = depacketizer = LiteEthUDPDepacketizer(dw) self.depacketizer = depacketizer = LiteEthUDPDepacketizer(dw)
# Data-Path. # Data-Path.
self.comb += [ self.comb += [
@ -178,7 +181,7 @@ class LiteEthUDPRX(Module):
# Control-Path (FSM). # Control-Path (FSM).
count = Signal(16) count = Signal(16)
self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE", fsm.act("IDLE",
NextValue(count, dw//8), NextValue(count, dw//8),
If(depacketizer.source.valid, If(depacketizer.source.valid,
@ -227,16 +230,16 @@ class LiteEthUDPRX(Module):
# UDP ---------------------------------------------------------------------------------------------- # UDP ----------------------------------------------------------------------------------------------
class LiteEthUDP(Module): class LiteEthUDP(LiteXModule):
def __init__(self, ip, ip_address, dw=8): def __init__(self, ip, ip_address, dw=8):
self.submodules.tx = tx = LiteEthUDPTX(ip_address, dw) self.tx = tx = LiteEthUDPTX(ip_address, dw)
self.submodules.rx = rx = LiteEthUDPRX(ip_address, dw) self.rx = rx = LiteEthUDPRX(ip_address, dw)
ip_port = ip.crossbar.get_port(udp_protocol, dw) ip_port = ip.crossbar.get_port(udp_protocol, dw)
self.comb += [ self.comb += [
tx.source.connect(ip_port.sink), tx.source.connect(ip_port.sink),
ip_port.source.connect(rx.sink) ip_port.source.connect(rx.sink)
] ]
self.submodules.crossbar = crossbar = LiteEthUDPCrossbar(dw) self.crossbar = crossbar = LiteEthUDPCrossbar(dw)
self.comb += [ self.comb += [
crossbar.master.source.connect(tx.sink), crossbar.master.source.connect(tx.sink),
rx.source.connect(crossbar.master.sink) rx.source.connect(crossbar.master.sink)