core/udp: Switch to LiteXModule.
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@ -1,14 +1,15 @@
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#
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# This file is part of LiteEth.
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#
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# Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2015-2023 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from liteeth.common import *
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from liteeth.crossbar import LiteEthCrossbar
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from litex.gen import *
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from litex.soc.interconnect import stream
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from liteeth.common import *
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from liteeth.crossbar import LiteEthCrossbar
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from liteeth.packet import Depacketizer, Packetizer
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# UDP Crossbar -------------------------------------------------------------------------------------
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@ -48,7 +49,7 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
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# ---
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# CDC.
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self.submodules.tx_cdc = tx_cdc = stream.ClockDomainCrossing(
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self.tx_cdc = tx_cdc = stream.ClockDomainCrossing(
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layout = eth_udp_user_description(user_port.dw),
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cd_from = cd,
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cd_to ="sys"
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@ -56,7 +57,7 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
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self.comb += user_port.sink.connect(tx_cdc.sink)
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# Data-Width Conversion.
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self.submodules.tx_converter = tx_converter = stream.StrideConverter(
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self.tx_converter = tx_converter = stream.StrideConverter(
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description_from = eth_udp_user_description(user_port.dw),
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description_to = eth_udp_user_description(self.dw)
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)
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@ -68,14 +69,14 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
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# RX
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# --
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# Data-Width Conversion.
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self.submodules.rx_converter = rx_converter = stream.StrideConverter(
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self.rx_converter = rx_converter = stream.StrideConverter(
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description_from = eth_udp_user_description(self.dw),
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description_to = eth_udp_user_description(user_port.dw)
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)
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self.comb += internal_port.source.connect(rx_converter.sink)
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# CDC.
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self.submodules.rx_cdc = rx_cdc = stream.ClockDomainCrossing(
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self.rx_cdc = rx_cdc = stream.ClockDomainCrossing(
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layout = eth_udp_user_description(user_port.dw),
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cd_from = "sys",
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cd_to = cd
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@ -98,10 +99,11 @@ class LiteEthUDPPacketizer(Packetizer):
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Packetizer.__init__(self,
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eth_udp_description(dw),
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eth_ipv4_user_description(dw),
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udp_header)
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udp_header
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)
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class LiteEthUDPTX(Module):
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class LiteEthUDPTX(LiteXModule):
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def __init__(self, ip_address, dw=8):
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self.sink = sink = stream.Endpoint(eth_udp_user_description(dw))
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self.source = source = stream.Endpoint(eth_ipv4_user_description(dw))
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@ -109,7 +111,7 @@ class LiteEthUDPTX(Module):
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# # #
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# Packetizer.
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self.submodules.packetizer = packetizer = LiteEthUDPPacketizer(dw=dw)
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self.packetizer = packetizer = LiteEthUDPPacketizer(dw=dw)
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# Data-Path.
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self.comb += [
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@ -126,7 +128,7 @@ class LiteEthUDPTX(Module):
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]
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# Control-Path (FSM).
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(packetizer.source.valid,
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NextState("SEND")
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@ -151,10 +153,11 @@ class LiteEthUDPDepacketizer(Depacketizer):
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Depacketizer.__init__(self,
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eth_ipv4_user_description(dw),
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eth_udp_description(dw),
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udp_header)
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udp_header
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)
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class LiteEthUDPRX(Module):
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class LiteEthUDPRX(LiteXModule):
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def __init__(self, ip_address, dw=8):
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self.sink = sink = stream.Endpoint(eth_ipv4_user_description(dw))
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self.source = source = stream.Endpoint(eth_udp_user_description(dw))
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@ -162,7 +165,7 @@ class LiteEthUDPRX(Module):
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# # #
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# Depacketizer.
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self.submodules.depacketizer = depacketizer = LiteEthUDPDepacketizer(dw)
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self.depacketizer = depacketizer = LiteEthUDPDepacketizer(dw)
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# Data-Path.
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self.comb += [
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@ -178,7 +181,7 @@ class LiteEthUDPRX(Module):
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# Control-Path (FSM).
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count = Signal(16)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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NextValue(count, dw//8),
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If(depacketizer.source.valid,
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@ -227,16 +230,16 @@ class LiteEthUDPRX(Module):
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# UDP ----------------------------------------------------------------------------------------------
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class LiteEthUDP(Module):
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class LiteEthUDP(LiteXModule):
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def __init__(self, ip, ip_address, dw=8):
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self.submodules.tx = tx = LiteEthUDPTX(ip_address, dw)
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self.submodules.rx = rx = LiteEthUDPRX(ip_address, dw)
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self.tx = tx = LiteEthUDPTX(ip_address, dw)
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self.rx = rx = LiteEthUDPRX(ip_address, dw)
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ip_port = ip.crossbar.get_port(udp_protocol, dw)
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self.comb += [
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tx.source.connect(ip_port.sink),
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ip_port.source.connect(rx.sink)
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]
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self.submodules.crossbar = crossbar = LiteEthUDPCrossbar(dw)
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self.crossbar = crossbar = LiteEthUDPCrossbar(dw)
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self.comb += [
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crossbar.master.source.connect(tx.sink),
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rx.source.connect(crossbar.master.sink)
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