From e83fd55fe850944e02ca34aea2b3dc6f70655b25 Mon Sep 17 00:00:00 2001 From: Arne Jansen Date: Tue, 27 Jun 2023 16:35:50 +0200 Subject: [PATCH] add tx_write_only flag This can save some resources in case reading the tx buffer is not needed. It also makes it easier for synthesis to infer BRAM, tested on Spartan6. --- liteeth/mac/__init__.py | 2 ++ liteeth/mac/wishbone.py | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/liteeth/mac/__init__.py b/liteeth/mac/__init__.py index b660e79..e1edaa7 100644 --- a/liteeth/mac/__init__.py +++ b/liteeth/mac/__init__.py @@ -18,6 +18,7 @@ class LiteEthMAC(Module, AutoCSR): with_preamble_crc = True, nrxslots = 2, ntxslots = 2, + tx_write_only = False, hw_mac = None, timestamp = None, full_memory_we = False, @@ -55,6 +56,7 @@ class LiteEthMAC(Module, AutoCSR): ntxslots = ntxslots, endianness = endianness, timestamp = timestamp, + tx_write_only = tx_write_only, ) # On some targets (Intel/Altera), the complex ports aren't inferred # as block ram, but are created with LUTs. FullMemoryWe splits such diff --git a/liteeth/mac/wishbone.py b/liteeth/mac/wishbone.py index f32b346..702a7a1 100644 --- a/liteeth/mac/wishbone.py +++ b/liteeth/mac/wishbone.py @@ -16,7 +16,7 @@ from litex.soc.interconnect import wishbone # MAC Wishbone Interface --------------------------------------------------------------------------- class LiteEthMACWishboneInterface(Module, AutoCSR): - def __init__(self, dw, nrxslots=2, ntxslots=2, endianness="big", timestamp=None): + def __init__(self, dw, nrxslots=2, ntxslots=2, endianness="big", timestamp=None, tx_write_only=False): self.sink = stream.Endpoint(eth_phy_description(dw)) self.source = stream.Endpoint(eth_phy_description(dw)) self.bus = wishbone.Interface(data_width=dw) @@ -43,7 +43,7 @@ class LiteEthMACWishboneInterface(Module, AutoCSR): for n in range(ntxslots): wb_tx_sram_ifs.append(wishbone.SRAM( mem_or_size = self.sram.reader.mems[n], - read_only = False, + write_only = tx_write_only, bus = wishbone.Interface(data_width = dw) ))