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phy/titaniumrgmii,trionrgmii: fixed pll clkin name by appending a '0' to match ClkInput / get_pin_name modifications introduces by LiteX commit d3161ad74c4b2afd5635f76f566c37f362eb166a

This commit is contained in:
Gwenhael Goavec-Merou 2024-09-04 14:48:34 +02:00
parent ecaebfe645
commit ea07f5c421
2 changed files with 2 additions and 2 deletions
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2
liteeth/phy/titaniumrgmii.py
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@ -143,7 +143,7 @@ class LiteEthPHYRGMIICRG(LiteXModule):
# TX PLL. # TX PLL.
# ------- # -------
self.pll = pll = TITANIUMPLL(platform) self.pll = pll = TITANIUMPLL(platform)
pll.register_clkin(None, freq=125e6, name=f"auto_eth{n}_rx_clk_in") pll.register_clkin(None, freq=125e6, name=f"auto_eth{n}_rx_clk_in0") # FIXME: 0 is to match ClkInput
pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, name=f"auto_eth{n}_rx_clk", with_reset=False) pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, name=f"auto_eth{n}_rx_clk", with_reset=False)
pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, name=f"auto_eth{n}_tx_clk", with_reset=False) pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, name=f"auto_eth{n}_tx_clk", with_reset=False)
pll.create_clkout(None, freq=125e6, phase=90, name=f"auto_eth{n}_tx_clk_delayed") pll.create_clkout(None, freq=125e6, phase=90, name=f"auto_eth{n}_tx_clk_delayed")

2
liteeth/phy/trionrgmii.py
View File

@ -143,7 +143,7 @@ class LiteEthPHYRGMIICRG(LiteXModule):
# TX PLL. # TX PLL.
# ------- # -------
self.pll = pll = TRIONPLL(platform) self.pll = pll = TRIONPLL(platform)
pll.register_clkin(None, freq=125e6, name=f"auto_eth{n}_rx_clk_in") pll.register_clkin(None, freq=125e6, name=f"auto_eth{n}_rx_clk_in0") # FIXME: 0 is to match ClkInput
pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, name=f"auto_eth{n}_rx_clk", with_reset=False, is_feedback=True) pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, name=f"auto_eth{n}_rx_clk", with_reset=False, is_feedback=True)
pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, name=f"auto_eth{n}_tx_clk", with_reset=False) pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, name=f"auto_eth{n}_tx_clk", with_reset=False)
pll.create_clkout(None, freq=125e6, phase=45, name=f"auto_eth{n}_tx_clk_delayed") pll.create_clkout(None, freq=125e6, phase=45, name=f"auto_eth{n}_tx_clk_delayed")