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frontend/stream/LiteEthStream2UDPTX: Latch ip_address/udp_port in Idle state. 

Useful when ip_address/udp_port are dynamic signals.
This commit is contained in:
Florent Kermarrec 2023-07-18 16:38:13 +02:00
parent 64cceb24b1
commit eb63b771a7
1 changed files with 8 additions and 3 deletions
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11
liteeth/frontend/stream.py
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@ -32,12 +32,17 @@ class LiteEthStream2UDPTX(LiteXModule):
level = Signal(max=fifo_depth+1) level = Signal(max=fifo_depth+1)
counter = Signal(max=fifo_depth+1) counter = Signal(max=fifo_depth+1)
_ip_address = Signal(32)
_udp_port = Signal(16)
self.fifo = fifo = stream.SyncFIFO([("data", data_width)], fifo_depth, buffered=True) self.fifo = fifo = stream.SyncFIFO([("data", data_width)], fifo_depth, buffered=True)
self.comb += sink.connect(fifo.sink) self.comb += sink.connect(fifo.sink)
self.fsm = fsm = FSM(reset_state="IDLE") self.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE", fsm.act("IDLE",
NextValue(counter, 0), NextValue(counter, 0),
NextValue(_ip_address, ip_address),
NextValue(_udp_port, udp_port),
# Send FIFO contenst when: # Send FIFO contenst when:
# - We have a full packet: # - We have a full packet:
If(fifo.sink.valid & fifo.sink.ready & fifo.sink.last, If(fifo.sink.valid & fifo.sink.ready & fifo.sink.last,
@ -53,9 +58,9 @@ class LiteEthStream2UDPTX(LiteXModule):
fsm.act("SEND", fsm.act("SEND",
source.valid.eq(1), source.valid.eq(1),
source.last.eq(counter == (level - 1)), source.last.eq(counter == (level - 1)),
source.src_port.eq(udp_port), source.src_port.eq(_udp_port),
source.dst_port.eq(udp_port), source.dst_port.eq(_udp_port),
source.ip_address.eq(ip_address), source.ip_address.eq(_ip_address),
source.length.eq(level * (data_width//8)), source.length.eq(level * (data_width//8)),
source.data.eq(fifo.source.data), source.data.eq(fifo.source.data),
source.last_be.eq({ source.last_be.eq({