mac/wishbone: Fix ntxslots/nrxslots == 1 case.

Previously, a common decoder was used for TX and RX slots, so there were at least
two interfaces connected. With the TX/RX decoupling, we now only have on interface
per decoder when ntxslots/nrxslots == 1.
This commit is contained in:
Florent Kermarrec 2024-07-02 13:50:06 +02:00
parent a00640bf67
commit ec7320f003
1 changed files with 2 additions and 2 deletions

View File

@ -72,10 +72,10 @@ class LiteEthMACWishboneInterface(LiteXModule):
wb_slaves = [] wb_slaves = []
sram_depth = math.ceil(eth_mtu/(dw//8)) sram_depth = math.ceil(eth_mtu/(dw//8))
decoderoffset = log2_int(sram_depth, need_pow2=False) decoderoffset = log2_int(sram_depth, need_pow2=False)
decoderbits = log2_int(len(wb_sram_ifs)) decoderbits = max(log2_int(len(wb_sram_ifs)), 1)
for n, wb_sram_if in enumerate(wb_sram_ifs): for n, wb_sram_if in enumerate(wb_sram_ifs):
def slave_filter(a, v=n): def slave_filter(a, v=n):
return a[decoderoffset:decoderoffset+decoderbits] == v return a[decoderoffset:decoderoffset + decoderbits] == v
wb_slaves.append((slave_filter, wb_sram_if.bus)) wb_slaves.append((slave_filter, wb_sram_if.bus))
self.submodules += wb_sram_if self.submodules += wb_sram_if
wb_con = wishbone.Decoder(bus, wb_slaves, register=True) wb_con = wishbone.Decoder(bus, wb_slaves, register=True)