From ecaebfe6451beed27edf14e083b718dbd2507c19 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Tue, 3 Sep 2024 15:06:46 +0200 Subject: [PATCH] phy/trionrgmii.py: fixed RX and TX sides. RX: forces phase align by usign it as PLL's feedback. TX: reduces PLL phase shift 90 -> 45 --- liteeth/phy/trionrgmii.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/liteeth/phy/trionrgmii.py b/liteeth/phy/trionrgmii.py index aec1abf..ba3dc99 100644 --- a/liteeth/phy/trionrgmii.py +++ b/liteeth/phy/trionrgmii.py @@ -144,9 +144,9 @@ class LiteEthPHYRGMIICRG(LiteXModule): # ------- self.pll = pll = TRIONPLL(platform) pll.register_clkin(None, freq=125e6, name=f"auto_eth{n}_rx_clk_in") - pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, name=f"auto_eth{n}_rx_clk", with_reset=False) + pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, name=f"auto_eth{n}_rx_clk", with_reset=False, is_feedback=True) pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, name=f"auto_eth{n}_tx_clk", with_reset=False) - pll.create_clkout(None, freq=125e6, phase=90, name=f"auto_eth{n}_tx_clk_delayed") + pll.create_clkout(None, freq=125e6, phase=45, name=f"auto_eth{n}_tx_clk_delayed") # Reset. # ------