From ee4f8c0f34ec0a08bac103a537cd8b7c3e42f17d Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 17 Jan 2020 09:15:51 +0100
Subject: [PATCH] phy/usrgmii: improve presentation

---
 liteeth/phy/usrgmii.py | 33 +++++++++++++++------------------
 1 file changed, 15 insertions(+), 18 deletions(-)

diff --git a/liteeth/phy/usrgmii.py b/liteeth/phy/usrgmii.py
index 585e0c9..725b723 100644
--- a/liteeth/phy/usrgmii.py
+++ b/liteeth/phy/usrgmii.py
@@ -15,7 +15,7 @@ class LiteEthPHYRGMIITX(Module):
 
         # # #
 
-        tx_ctl_obuf = Signal()
+        tx_ctl_obuf  = Signal()
         tx_data_obuf = Signal(4)
 
         self.specials += [
@@ -50,12 +50,12 @@ class LiteEthPHYRGMIIRX(Module):
 
         # # #
 
-        rx_ctl_ibuf = Signal()
-        rx_ctl_idelay = Signal()
-        rx_ctl = Signal()
-        rx_data_ibuf = Signal(4)
+        rx_ctl_ibuf    = Signal()
+        rx_ctl_idelay  = Signal()
+        rx_ctl         = Signal()
+        rx_data_ibuf   = Signal(4)
         rx_data_idelay = Signal(4)
-        rx_data = Signal(8)
+        rx_data        = Signal(8)
 
         self.specials += [
             Instance("IBUF", i_I=pads.rx_ctl, o_O=rx_ctl_ibuf),
@@ -137,8 +137,8 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
 
         # # #
 
-        self.clock_domains.cd_eth_rx = ClockDomain()
-        self.clock_domains.cd_eth_tx = ClockDomain()
+        self.clock_domains.cd_eth_rx   = ClockDomain()
+        self.clock_domains.cd_eth_tx   = ClockDomain()
         self.clock_domains.cd_eth_tx90 = ClockDomain(reset_less=True)
 
         # RX
@@ -153,10 +153,10 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
         ]
 
         # TX
-        pll_locked = Signal()
-        pll_fb = Signal()
-        pll_clk_tx = Signal()
-        pll_clk_tx90 = Signal()
+        pll_locked      = Signal()
+        pll_fb          = Signal()
+        pll_clk_tx      = Signal()
+        pll_clk_tx90    = Signal()
         eth_tx_clk_obuf = Signal()
         self.specials += [
             Instance("PLLE2_BASE",
@@ -212,12 +212,9 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
 class LiteEthPHYRGMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
         self.dw = 8
-        self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads,
-                                                 with_hw_init_reset)
-        self.submodules.tx = ClockDomainsRenamer("eth_tx")(
-            LiteEthPHYRGMIITX(pads))
-        self.submodules.rx = ClockDomainsRenamer("eth_rx")(
-            LiteEthPHYRGMIIRX(pads))
+        self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset)
+        self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
+        self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
         self.sink, self.source = self.tx.sink, self.rx.source
 
         if hasattr(pads, "mdc"):