From ef214571d5761f738d3cb3bdf3a50261d87a00a9 Mon Sep 17 00:00:00 2001 From: David Sawatzke Date: Sun, 8 Aug 2021 17:44:24 +0200 Subject: [PATCH] mac/core: Move preamble into switchable domain --- liteeth/mac/core.py | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/liteeth/mac/core.py b/liteeth/mac/core.py index 552ca20..0314f32 100644 --- a/liteeth/mac/core.py +++ b/liteeth/mac/core.py @@ -37,6 +37,11 @@ class LiteEthMACCore(Module, AutoCSR): self.submodules += ClockDomainsRenamer(cd_tx)(tx_gap_inserter) tx_pipeline += [tx_gap_inserter] + if sys_data_path: + self.data_path_converter(tx_pipeline, rx_pipeline, core_dw, phy.dw, endianness) + cd_tx = cd_rx = "sys" + dw = core_dw + # Preamble / CRC if isinstance(phy, LiteEthPHYModel): # In simulation, avoid CRC/Preamble to enable direct connection @@ -61,12 +66,6 @@ class LiteEthMACCore(Module, AutoCSR): self.sync += If(self.ps_preamble_error.o, self.preamble_errors.status.eq(self.preamble_errors.status + 1)), - if sys_data_path: - self.data_path_converter(tx_pipeline, rx_pipeline, core_dw, phy.dw, endianness) - cd_tx = cd_rx = "sys" - dw = core_dw - - if not isinstance(phy, LiteEthPHYModel) and with_preamble_crc: # CRC insert/check crc32_inserter = BufferizeEndpoints({"sink": DIR_SINK})(crc.LiteEthMACCRC32Inserter(eth_phy_description(dw))) crc32_checker = BufferizeEndpoints({"sink": DIR_SINK})(crc.LiteEthMACCRC32Checker(eth_phy_description(dw)))