From f00d95c534885f23d21def41ab90daadc1969360 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 8 Jun 2023 17:56:37 +0200 Subject: [PATCH] usp_1000basex: Update a few parameter and add debug probes to investigate on xcu1525. --- bench/xcu1525.py | 22 ++++++++++++++++++++-- liteeth/phy/ku_1000basex.py | 2 -- liteeth/phy/usp_1000basex.py | 30 ++++++++++++++++++++++++------ 3 files changed, 44 insertions(+), 10 deletions(-) diff --git a/bench/xcu1525.py b/bench/xcu1525.py index a34d696..6082481 100755 --- a/bench/xcu1525.py +++ b/bench/xcu1525.py @@ -63,6 +63,9 @@ class BenchSoC(SoCCore): ident_version = True ) + # UARTBone --------------------------------------------------------------------------------- + self.add_uartbone() + # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -70,7 +73,7 @@ class BenchSoC(SoCCore): self.submodules.ethphy = USP_1000BASEX(self.crg.cd_eth.clk, data_pads = self.platform.request("qsfp", 0), sys_clk_freq = self.clk_freq) - self.comb += self.platform.request("qsfp_fs").eq(0b01) + #self.comb += self.platform.request("qsfp_fs").eq(0b01) self.add_etherbone(phy=self.ethphy, buffer_depth=255) # SRAM ------------------------------------------------------------------------------------- @@ -80,7 +83,22 @@ class BenchSoC(SoCCore): from litex.soc.cores.led import LedChaser self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), - sys_clk_freq = sys_clk_freq) + sys_clk_freq = sys_clk_freq + ) + + # Litescope -------------------------------------------------------------------------------- + + from litescope import LiteScopeAnalyzer + analyzer_signals = self.ethphy.debug + self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, + depth = 256, + clock_domain = "sys", + csr_csv = "analyzer.csv" + ) + + + + # Main --------------------------------------------------------------------------------------------- diff --git a/liteeth/phy/ku_1000basex.py b/liteeth/phy/ku_1000basex.py index 2f7baf7..74b40a1 100644 --- a/liteeth/phy/ku_1000basex.py +++ b/liteeth/phy/ku_1000basex.py @@ -646,8 +646,6 @@ class KU_1000BASEX(Module, AutoCSR): i_RXUSERRDY = 0b1, i_RXUSRCLK2 = ClockSignal("eth_rx_half"), i_RXUSRCLK = ClockSignal("eth_rx_half"), - #i_SATA_BURST = 0b100, - #i_SATA_EIDLE = 0b100, i_SIGVALIDCLK = 0b0, i_TSTIN = 0b00000000000000000000, i_TX8B10BBYPASS = 0b00000000, diff --git a/liteeth/phy/usp_1000basex.py b/liteeth/phy/usp_1000basex.py index e2e33df..47c6d7a 100644 --- a/liteeth/phy/usp_1000basex.py +++ b/liteeth/phy/usp_1000basex.py @@ -153,8 +153,8 @@ class USP_1000BASEX(Module, AutoCSR): p_CLK_COR_SEQ_1_ENABLE = 0b1111, p_CLK_COR_SEQ_2_1 = 0b0010111100, p_CLK_COR_SEQ_2_2 = 0b0010110101, - p_CLK_COR_SEQ_2_3 = 0b0000000000, - p_CLK_COR_SEQ_2_4 = 0b0000000000, + p_CLK_COR_SEQ_2_3 = 0b0100000000, + p_CLK_COR_SEQ_2_4 = 0b0100000000, p_CLK_COR_SEQ_2_ENABLE = 0b1111, p_CLK_COR_SEQ_2_USE = "TRUE", p_CLK_COR_SEQ_LEN = 2, @@ -213,7 +213,7 @@ class USP_1000BASEX(Module, AutoCSR): p_ES_SDATA_MASK7 = 0b0000000000000000, p_ES_SDATA_MASK8 = 0b0000000000000000, p_ES_SDATA_MASK9 = 0b0000000000000000, - p_EYESCAN_VP_RANGE = 0, + p_EYESCAN_VP_RANGE = 0b0, p_EYE_SCAN_SWAP_EN = 0b0, p_FTS_DESKEW_SEQ_ENABLE = 0b1111, p_FTS_LANE_DESKEW_CFG = 0b1111, @@ -398,7 +398,7 @@ class USP_1000BASEX(Module, AutoCSR): p_RXSLIDE_MODE = "OFF", p_RXSYNC_MULTILANE = 0b0, p_RXSYNC_OVRD = 0b0, - p_RXSYNC_SKIP_DA = 0b0, + p_RXSYNC_SKIP_DA = 0b1, p_RX_AFE_CM_EN = 0b0, p_RX_BIAS_CFG0 = 0b0001001010110000, p_RX_BUFFER_CFG = 0b000000, @@ -464,7 +464,9 @@ class USP_1000BASEX(Module, AutoCSR): p_SAMPLE_CLK_PHASE = 0b0, p_SAS_12G_MODE = 0b0, p_SATA_BURST_SEQ_LEN = 0b1111, + p_SATA_BURST_VAL = 0b100, p_SATA_CPLL_CFG = "VCO_3000MHZ", + p_SATA_EIDLE_VAL = 0b100, p_SHOW_REALIGN_COMMA = "TRUE", p_SIM_DEVICE = "ULTRASCALE_PLUS", p_SIM_MODE = "FAST", @@ -504,6 +506,7 @@ class USP_1000BASEX(Module, AutoCSR): p_TXPI_PPM = 0b0, p_TXPI_PPM_CFG = 0b00000000, p_TXPI_SYNFREQ_PPM = 0b001, + p_TXPMARESET_TIME = 0b00011, p_TXREFCLKDIV2_SEL = 0b0, p_TXSWBST_BST = 1, p_TXSWBST_EN = 0, @@ -598,7 +601,7 @@ class USP_1000BASEX(Module, AutoCSR): i_CPLLLOCKDETCLK = 0b0, i_CPLLLOCKEN = 0b1, i_CPLLPD = pll_reset, - i_CPLLREFCLKSEL = 0b001, + i_CPLLREFCLKSEL = 0b111, i_CPLLRESET = 0b0, i_DMONFIFORESET = 0b0, i_DMONITORCLK = 0b0, @@ -807,7 +810,7 @@ class USP_1000BASEX(Module, AutoCSR): i_TXPOSTCURSOR = 0b00000, i_TXPRBSFORCEERR = 0b0, i_TXPRBSSEL = 0b0000, - i_TXPRECURSOR =0b00000, + i_TXPRECURSOR = 0b00000, i_TXPROGDIVRESET = 0b0, i_TXRATE = 0b000, i_TXRATEMODE = 0b0, @@ -984,3 +987,18 @@ class USP_1000BASEX(Module, AutoCSR): gearbox.tx_data.eq(pcs.tbi_tx), pcs.tbi_rx.eq(gearbox.rx_data) ] + + self.debug = [ + gtpowergood, + pll_reset, + pll_locked, + tx_reset, + tx_data, + tx_reset_done, + rx_reset, + rx_data, + rx_reset_done, + self.sink, + self.source, + self.link_up + ]