Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

core/arp: Only increment clear_timer in IDLE state and change timeout to 1s.

This commit is contained in:
Florent Kermarrec 2023-08-02 14:54:32 +02:00
parent cb1e1932b3
commit f0c876ca77
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
liteeth/core/arp.py
View File

@ -196,9 +196,8 @@ class LiteEthARPCache(LiteXModule):
mem_rd_port_ip_address = mem_rd_port.dat_r[0:32] mem_rd_port_ip_address = mem_rd_port.dat_r[0:32]
mem_rd_port_mac_address = mem_rd_port.dat_r[32:80] mem_rd_port_mac_address = mem_rd_port.dat_r[32:80]
# Clear Timer to clear table every 100ms. # Clear Timer to clear table every 1s.
self.clear_timer = WaitTimer(100e-3*clk_freq) self.clear_timer = WaitTimer(1e-0*clk_freq)
self.comb += self.clear_timer.wait.eq(~self.clear_timer.done)
# FSM. # FSM.
self.fsm = fsm = FSM(reset_state="CLEAR") self.fsm = fsm = FSM(reset_state="CLEAR")
@ -219,7 +218,8 @@ class LiteEthARPCache(LiteXModule):
NextValue(search_count, 0), NextValue(search_count, 0),
NextState("MEM_SEARCH") NextState("MEM_SEARCH")
), ),
If(self.clear_enable & self.clear_timer.done, self.clear_timer.wait.eq(self.clear_enable),
If(self.clear_timer.done,
NextValue(update_count, 0), NextValue(update_count, 0),
NextState("CLEAR") NextState("CLEAR")
) )