From f192183255adb527614770394fa863af98f28543 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 27 Jun 2022 15:35:37 +0200 Subject: [PATCH] liteeth/gen: Revert and fix missing Wishbone interface. --- liteeth/gen.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/liteeth/gen.py b/liteeth/gen.py index b1fd69d..2064c72 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -242,6 +242,11 @@ class MACCore(PHYCore): full_memory_we = core_config.get("full_memory_we", False)) # Wishbone Interface ----------------------------------------------------------------------- + wb_bus = wishbone.Interface() + platform.add_extension(wb_bus.get_ios("wishbone")) + self.comb += wb_bus.connect_to_pads(self.platform.request("wishbone"), mode="slave") + self.add_wb_master(wb_bus) + ethmac_region_size = (nrxslots + ntxslots)*buffer_depth ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False) self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region)