From f2032a422791a73d9950c6d8faff0b26dfbc956d Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 23 Sep 2021 12:24:58 +1000 Subject: [PATCH] Remove clock asserts They aren't strictly necessary, especially since the MAC can have a wider data path and thus cope with running slightly slower Signed-off-by: Benjamin Herrenschmidt --- liteeth/gen.py | 5 ----- 1 file changed, 5 deletions(-) diff --git a/liteeth/gen.py b/liteeth/gen.py index d150d23..ebfb36a 100755 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -179,28 +179,23 @@ class PHYCore(SoCMini): # PHY -------------------------------------------------------------------------------------- phy = core_config["phy"] if phy in [liteeth_phys.LiteEthPHYMII]: - assert self.clk_freq >= 12.5e6 ethphy = phy( clock_pads = platform.request("mii_eth_clocks"), pads = platform.request("mii_eth")) elif phy in [liteeth_phys.LiteEthPHYRMII]: - assert self.clk_freq >= 12.5e6 ethphy = phy( clock_pads = platform.request("rmii_eth_clocks"), pads = platform.request("rmii_eth")) elif phy in [liteeth_phys.LiteEthPHYGMII]: - assert self.clk_freq >= 125e6 ethphy = phy( clock_pads = platform.request("gmii_eth_clocks"), pads = platform.request("gmii_eth")) elif phy in [liteeth_phys.LiteEthPHYGMIIMII]: - assert self.clk_freq >= 125e6 ethphy = phy( clock_pads = platform.request("gmii_eth_clocks"), pads = platform.request("gmii_eth"), clk_freq = self.clk_freq) elif phy in [liteeth_phys.LiteEthS7PHYRGMII, liteeth_phys.LiteEthECP5PHYRGMII]: - assert self.clk_freq >= 125e6 ethphy = phy( clock_pads = platform.request("rgmii_eth_clocks"), pads = platform.request("rgmii_eth"),