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phy/rmii/LiteEthPHYRMIIRX: Avoid FSM, simplify and add comments.

This commit is contained in:
Florent Kermarrec 2024-09-23 14:55:10 +02:00
parent 5438ff01e1
commit f252eed154
1 changed files with 22 additions and 20 deletions
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42
liteeth/phy/rmii.py
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@ -40,6 +40,7 @@ class LiteEthPHYRMIITX(LiteXModule):
for i in range(2): for i in range(2):
self.specials += SDROutput(i=converter.source.data[i], o=pads.tx_data[i]) self.specials += SDROutput(i=converter.source.data[i], o=pads.tx_data[i])
# LiteEth PHY RMII RX ------------------------------------------------------------------------------ # LiteEth PHY RMII RX ------------------------------------------------------------------------------
class LiteEthPHYRMIIRX(LiteXModule): class LiteEthPHYRMIIRX(LiteXModule):
@ -62,6 +63,8 @@ class LiteEthPHYRMIIRX(LiteXModule):
# Delay. # Delay.
# ------ # ------
# Add a delay to align the data with the frame boundaries since the end-of-frame condition
# (2 consecutive `crs_dv` signals low) is detected with a few cycles delay.
self.delay = delay = stream.Delay(layout=[("data", 8)], n=2) self.delay = delay = stream.Delay(layout=[("data", 8)], n=2)
# Frame Delimitation. # Frame Delimitation.
@ -69,31 +72,30 @@ class LiteEthPHYRMIIRX(LiteXModule):
crs_dv_d = Signal() crs_dv_d = Signal()
crs_first = Signal() crs_first = Signal()
crs_last = Signal() crs_last = Signal()
crs_run = Signal()
self.sync += crs_dv_d.eq(crs_dv) self.sync += crs_dv_d.eq(crs_dv)
self.comb += [ self.comb += [
crs_first.eq(crs_dv & (rx_data != 0b00)), # Start of frame on crs_dv at 1 and non-null data. crs_first.eq(crs_dv & (rx_data != 0b00)), # Start of frame on crs_dv high and non-null data.
crs_last.eq(~crs_dv & ~crs_dv_d), # End of frame on 2 consecutives crs_dv at 0. crs_last.eq(~crs_dv & ~crs_dv_d), # End of frame on 2 consecutive crs_dv low.
]
self.sync += [
If(crs_first, crs_run.eq(1)),
If(crs_last, crs_run.eq(0)),
] ]
self.fsm = fsm = FSM(reset_state="IDLE") # Datapath: Input -> Delay -> Converter -> Source.
fsm.act("IDLE", # ------------------------------------------------
delay.source.ready.eq(1), self.comb += [
If(crs_first, delay.source.ready.eq(1), # Ready by default to flush pipeline.
delay.sink.valid.eq(1), delay.sink.valid.eq(crs_first | crs_run),
delay.sink.data.eq(rx_data), delay.sink.data.eq(rx_data),
NextState("RECEIVE") If(crs_run,
) converter.sink.last.eq(crs_last),
) delay.source.connect(converter.sink, keep={"valid", "ready", "data"})
fsm.act("RECEIVE", ),
delay.sink.valid.eq(1), converter.source.connect(source),
delay.sink.data.eq(rx_data), ]
delay.source.connect(converter.sink),
If(crs_last,
converter.sink.last.eq(1),
NextState("IDLE")
)
)
self.comb += converter.source.connect(source)
# LiteEth PHY RMII CRG ----------------------------------------------------------------------------- # LiteEth PHY RMII CRG -----------------------------------------------------------------------------