diff --git a/liteeth/phy/common.py b/liteeth/phy/common.py
index a290dfb..1738e9c 100644
--- a/liteeth/phy/common.py
+++ b/liteeth/phy/common.py
@@ -6,15 +6,16 @@ from liteeth.common import *
 from migen.genlib.cdc import MultiReg
 from migen.fhdl.specials import Tristate
 
+
 class LiteEthPHYHWReset(Module):
     def __init__(self):
         self.reset = Signal()
 
         # # #
 
-        counter = Signal(max=512)
+        counter      = Signal(max=512)
         counter_done = Signal()
-        counter_ce = Signal()
+        counter_ce   = Signal()
         self.sync += If(counter_ce, counter.eq(counter + 1))
         self.comb += [
             counter_done.eq(counter == 256),
@@ -25,14 +26,21 @@ class LiteEthPHYHWReset(Module):
 
 class LiteEthPHYMDIO(Module, AutoCSR):
     def __init__(self, pads):
-        self._w = CSRStorage(3, name="w")
-        self._r = CSRStatus(1, name="r")
+        self._w = CSRStorage(fields=[
+            CSRField("mdc", size=1),
+            CSRField("oe",  size=1),
+            CSRField("w",   size=1)],
+            name="w")
+        self._r = CSRStatus(fields=[
+            CSRField("r", size=1)],
+            name="r")
+
 
         # # #
 
-        data_w = Signal()
+        data_w  = Signal()
         data_oe = Signal()
-        data_r = Signal()
+        data_r  = Signal()
         self.comb +=[
             pads.mdc.eq(self._w.storage[0]),
             data_oe.eq(self._w.storage[1]),