diff --git a/liteeth/core/mac/sram.py b/liteeth/core/mac/sram.py
index b33d71c..5a071f0 100644
--- a/liteeth/core/mac/sram.py
+++ b/liteeth/core/mac/sram.py
@@ -167,22 +167,14 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
 
         # fsm
         last  = Signal()
-        last_d = Signal()
 
         fsm = FSM(reset_state="IDLE")
         self.submodules += fsm
 
         fsm.act("IDLE",
-            counter_reset.eq(1),
             If(fifo.source.valid,
-                NextState("CHECK")
-            )
-        )
-        fsm.act("CHECK",
-            If(~last_d,
-                NextState("SEND"),
-            ).Else(
-                NextState("END"),
+                counter_ce.eq(1),
+                NextState("SEND")
             )
         )
         length_lsb = fifo.source.length[0:2]
@@ -203,19 +195,21 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
             source.valid.eq(1),
             source.last.eq(last),
             If(source.ready,
-                counter_ce.eq(~last),
-                NextState("CHECK")
+                counter_ce.eq(1),
+                If(last,
+                    NextState("TERMINATE")
+                )
             )
         )
-        fsm.act("END",
+        fsm.act("TERMINATE",
             fifo.source.ready.eq(1),
             self.ev.done.trigger.eq(1),
+            counter_reset.eq(1),
             NextState("IDLE")
         )
 
         # last computation
-        self.comb += last.eq((counter + 4) >= fifo.source.length)
-        self.sync += last_d.eq(last)
+        self.comb += last.eq(counter >= fifo.source.length)
 
         # memory
         rd_slot = fifo.source.slot
diff --git a/test/mac_wishbone_tb.py b/test/mac_wishbone_tb.py
index cad9056..7730154 100755
--- a/test/mac_wishbone_tb.py
+++ b/test/mac_wishbone_tb.py
@@ -142,7 +142,7 @@ if __name__ == "__main__":
                    tb.phy_model.generator()],
         "eth_rx":  tb.phy_model.phy_source.generator()
     }
-    clocks = {"sys":    10,
-              "eth_rx": 10,
-              "eth_tx": 10}
+    clocks = {"sys":    20,
+              "eth_rx": 8,
+              "eth_tx": 8}
     run_simulation(tb, generators, clocks, vcd_name="sim.vcd")