From f6d8ddbba028a7a65368ae13facb5f4214761efd Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 19 Apr 2017 10:39:52 +0200 Subject: [PATCH] update litex uart --- example_designs/targets/base.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/example_designs/targets/base.py b/example_designs/targets/base.py index 38c7f4a..485109a 100644 --- a/example_designs/targets/base.py +++ b/example_designs/targets/base.py @@ -4,7 +4,7 @@ from litex.build.xilinx.vivado import XilinxVivadoToolchain from litex.soc.interconnect import wishbone from litex.soc.integration.soc_core import SoCCore -from litex.soc.cores.uart.bridge import UARTWishboneBridge +from litex.soc.cores.uart import UARTWishboneBridge from liteeth.common import * from liteeth.phy import LiteEthPHY