diff --git a/bench/arty.py b/bench/arty.py index 4bb88fc..f2fbea1 100755 --- a/bench/arty.py +++ b/bench/arty.py @@ -3,7 +3,7 @@ # # This file is part of LiteEth. # -# Copyright (c) 2020 Florent Kermarrec +# Copyright (c) 2020-2023 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause import os @@ -13,6 +13,8 @@ from migen import * from migen.genlib.cdc import MultiReg from migen.genlib.misc import WaitTimer +from litex.gen import * + from litex_boards.platforms import digilent_arty from litex_boards.targets.digilent_arty import _CRG @@ -37,10 +39,10 @@ class BenchSoC(SoCCore): ) # CRG -------------------------------------------------------------------------------------- - self.submodules.crg = _CRG(platform, sys_clk_freq) + self.crg = _CRG(platform, sys_clk_freq) # Etherbone -------------------------------------------------------------------------------- - self.submodules.ethphy = LiteEthPHYMII( + self.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth"), with_hw_init_reset = False) @@ -51,8 +53,8 @@ class BenchSoC(SoCCore): # UDP Streamer ----------------------------------------------------------------------------- from liteeth.frontend.stream import LiteEthUDPStreamer - self.submodules.udp_streamer = udp_streamer = LiteEthUDPStreamer( - udp = self.ethcore.udp, + self.udp_streamer = udp_streamer = LiteEthUDPStreamer( + udp = self.ethcore_etherbone.udp, ip_address = "192.168.1.100", udp_port = 6000, ) @@ -62,7 +64,7 @@ class BenchSoC(SoCCore): # Led Chaser (Default). chaser_leds = Signal(len(leds_pads)) - self.submodules.leds = LedChaser( + self.leds = LedChaser( pads = chaser_leds, sys_clk_freq = sys_clk_freq) @@ -74,7 +76,7 @@ class BenchSoC(SoCCore): ) # Led Mux: Switch to received UDP value for 1s then switch back to Led Chaser. - self.submodules.leds_timer = leds_timer = WaitTimer(sys_clk_freq) + self.leds_timer = leds_timer = WaitTimer(sys_clk_freq) self.comb += [ leds_timer.wait.eq(~udp_streamer.rx.source.valid), # Reload Timer on new UDP value. If(leds_timer.done, diff --git a/bench/butterstick.py b/bench/butterstick.py index 1b76600..70c44ae 100755 --- a/bench/butterstick.py +++ b/bench/butterstick.py @@ -3,7 +3,7 @@ # # This file is part of LiteEth. # -# Copyright (c) 2022 Florent Kermarrec +# Copyright (c) 2022-2023 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause import os @@ -11,6 +11,8 @@ import argparse from migen import * +from litex.gen import * + from litex_boards.platforms import gsd_butterstick from litex_boards.targets.gsd_butterstick import _CRG @@ -34,10 +36,10 @@ class BenchSoC(SoCCore): ) # CRG -------------------------------------------------------------------------------------- - self.submodules.crg = _CRG(platform, sys_clk_freq) + self.crg = _CRG(platform, sys_clk_freq) # Etherbone -------------------------------------------------------------------------------- - self.submodules.ethphy = LiteEthPHYRGMII( + self.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth"), tx_delay = 0e-9, @@ -50,7 +52,7 @@ class BenchSoC(SoCCore): # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser self.comb += platform.request("user_led_color").eq(0b010) # Blue. - self.submodules.leds = LedChaser( + self.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq ) @@ -62,7 +64,7 @@ class BenchSoC(SoCCore): from litescope import LiteScopeAnalyzer ethcore = self.ethcore_etherbone etherbone = self.etherbone - self.submodules.analyzer = LiteScopeAnalyzer([ + self.analyzer = LiteScopeAnalyzer([ # MAC. ethcore.mac.core.sink.valid, ethcore.mac.core.sink.ready, diff --git a/bench/colorlight_5a_75b.py b/bench/colorlight_5a_75b.py index 534855a..b7f5166 100755 --- a/bench/colorlight_5a_75b.py +++ b/bench/colorlight_5a_75b.py @@ -3,7 +3,7 @@ # # This file is part of LiteEth. # -# Copyright (c) 2020 Florent Kermarrec +# Copyright (c) 2020-2023 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause import os @@ -11,6 +11,8 @@ import argparse from migen import * +from litex.gen import * + from litex_boards.platforms import colorlight_5a_75b from litex_boards.targets.colorlight_5a_75x import _CRG @@ -34,10 +36,10 @@ class BenchSoC(SoCCore): ) # CRG -------------------------------------------------------------------------------------- - self.submodules.crg = _CRG(platform, sys_clk_freq) + self.crg = _CRG(platform, sys_clk_freq) # Etherbone -------------------------------------------------------------------------------- - self.submodules.ethphy = LiteEthPHYRGMII( + self.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth"), tx_delay = 0e-9, @@ -49,7 +51,7 @@ class BenchSoC(SoCCore): # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser - self.submodules.leds = LedChaser( + self.leds = LedChaser( pads = platform.request_all("user_led_n"), sys_clk_freq = sys_clk_freq) diff --git a/bench/genesys2.py b/bench/genesys2.py index 3fc6db8..08e25c2 100755 --- a/bench/genesys2.py +++ b/bench/genesys2.py @@ -3,7 +3,7 @@ # # This file is part of LiteEth. # -# Copyright (c) 2020 Florent Kermarrec +# Copyright (c) 2020-2023 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause import os @@ -11,6 +11,8 @@ import argparse from migen import * +from litex.gen import * + from litex_boards.platforms import digilent_genesys2 from litex_boards.targets.digilent_genesys2 import _CRG @@ -34,10 +36,10 @@ class BenchSoC(SoCCore): ) # CRG -------------------------------------------------------------------------------------- - self.submodules.crg = _CRG(platform, sys_clk_freq) + self.crg = _CRG(platform, sys_clk_freq) # Etherbone -------------------------------------------------------------------------------- - self.submodules.ethphy = LiteEthPHYRGMII( + self.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth"), with_hw_init_reset = False) @@ -48,7 +50,7 @@ class BenchSoC(SoCCore): # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser - self.submodules.leds = LedChaser( + self.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) diff --git a/bench/kcu105.py b/bench/kcu105.py index 34b676a..206fd6b 100755 --- a/bench/kcu105.py +++ b/bench/kcu105.py @@ -3,7 +3,7 @@ # # This file is part of LiteEth. # -# Copyright (c) 2021 Florent Kermarrec +# Copyright (c) 2021-2023 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause import os @@ -12,6 +12,8 @@ import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer +from litex.gen import * + from litex_boards.platforms import xilinx_kcu105 from litex.soc.cores.clock import * @@ -23,15 +25,15 @@ from liteeth.phy.ku_1000basex import KU_1000BASEX # CRG ---------------------------------------------------------------------------------------------- -class _CRG(Module, AutoCSR): +class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_eth = ClockDomain() + self.cd_sys = ClockDomain() + self.cd_eth = ClockDomain() # # # # Main PLL. - self.submodules.main_pll = main_pll = USMMCM(speedgrade=-2) + self.main_pll = main_pll = USMMCM(speedgrade=-2) self.comb += main_pll.reset.eq(platform.request("cpu_reset")) main_pll.register_clkin(platform.request("clk125"), 125e6) main_pll.create_clkout(self.cd_sys, sys_clk_freq) @@ -50,10 +52,10 @@ class BenchSoC(SoCCore): ) # CRG -------------------------------------------------------------------------------------- - self.submodules.crg = _CRG(platform, sys_clk_freq) + self.crg = _CRG(platform, sys_clk_freq) # Etherbone -------------------------------------------------------------------------------- - self.submodules.ethphy = KU_1000BASEX(self.crg.cd_eth.clk, + self.ethphy = KU_1000BASEX(self.crg.cd_eth.clk, data_pads = self.platform.request("sfp", 0), sys_clk_freq = self.clk_freq) self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1) @@ -65,7 +67,7 @@ class BenchSoC(SoCCore): # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser - self.submodules.leds = LedChaser( + self.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) diff --git a/bench/sim.py b/bench/sim.py index bedddf1..efd8a49 100755 --- a/bench/sim.py +++ b/bench/sim.py @@ -3,13 +3,15 @@ # # This file is part of LiteEth. # -# Copyright (c) 2020 Florent Kermarrec +# Copyright (c) 2020-2023 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause import argparse from migen import * +from litex.gen import * + from litex.build.generic_platform import * from litex.build.sim import SimPlatform from litex.build.sim.config import SimConfig @@ -22,8 +24,10 @@ from liteeth.phy.model import LiteEthPHYModel # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Sys Clk/Rst. ("sys_clk", 0, Pins(1)), ("sys_rst", 0, Pins(1)), + # Ethernet. ("eth_clocks", 0, Subsignal("tx", Pins(1)), Subsignal("rx", Pins(1)), @@ -59,10 +63,10 @@ class BenchSoC(SoCCore): ) # CRG -------------------------------------------------------------------------------------- - self.submodules.crg = CRG(platform.request("sys_clk")) + self.crg = CRG(platform.request("sys_clk")) # Etherbone -------------------------------------------------------------------------------- - self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth")) + self.ethphy = LiteEthPHYModel(self.platform.request("eth")) self.add_etherbone(phy=self.ethphy, buffer_depth=255) # SRAM ------------------------------------------------------------------------------------- diff --git a/bench/test_etherbone.py b/bench/test_etherbone.py index f1661c4..4394e7f 100755 --- a/bench/test_etherbone.py +++ b/bench/test_etherbone.py @@ -3,7 +3,7 @@ # # This file is part of LiteEth # -# Copyright (c) 2020 Florent Kermarrec +# Copyright (c) 2020-2023 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause # LiteEth Etherbone test utility. diff --git a/bench/test_udp_streamer.py b/bench/test_udp_streamer.py index d7d881b..35a6220 100755 --- a/bench/test_udp_streamer.py +++ b/bench/test_udp_streamer.py @@ -3,7 +3,7 @@ # # This file is part of LiteEth # -# Copyright (c) 2021 Florent Kermarrec +# Copyright (c) 2021-2023 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause # LiteEth UDP Streamer test utility. diff --git a/bench/xcu1525.py b/bench/xcu1525.py index d6575eb..c7f2e36 100755 --- a/bench/xcu1525.py +++ b/bench/xcu1525.py @@ -3,7 +3,7 @@ # # This file is part of LiteEth. # -# Copyright (c) 2021 Florent Kermarrec +# Copyright (c) 2021-2023 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause import os @@ -12,6 +12,8 @@ import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer +from litex.gen import * + from litex.build.generic_platform import * from litex_boards.platforms import sqrl_xcu1525 @@ -37,15 +39,15 @@ _qsfp_io = [ # CRG ---------------------------------------------------------------------------------------------- -class _CRG(Module, AutoCSR): +class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_eth = ClockDomain() + self.cd_sys = ClockDomain() + self.cd_eth = ClockDomain() # # # # Main PLL. - self.submodules.main_pll = main_pll = USPMMCM(speedgrade=-2) + self.main_pll = main_pll = USPMMCM(speedgrade=-2) main_pll.register_clkin(platform.request("clk300"), 300e6) main_pll.create_clkout(self.cd_sys, sys_clk_freq) main_pll.create_clkout(self.cd_eth, 200e6) @@ -67,10 +69,10 @@ class BenchSoC(SoCCore): self.add_uartbone() # CRG -------------------------------------------------------------------------------------- - self.submodules.crg = _CRG(platform, sys_clk_freq) + self.crg = _CRG(platform, sys_clk_freq) # Etherbone -------------------------------------------------------------------------------- - self.submodules.ethphy = USP_1000BASEX(self.crg.cd_eth.clk, + self.ethphy = USP_1000BASEX(self.crg.cd_eth.clk, data_pads = self.platform.request("qsfp", 0), sys_clk_freq = self.clk_freq) self.comb += self.platform.request("qsfp_fs").eq(0b01) @@ -81,7 +83,7 @@ class BenchSoC(SoCCore): # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser - self.submodules.leds = LedChaser( + self.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq ) @@ -90,7 +92,7 @@ class BenchSoC(SoCCore): from litescope import LiteScopeAnalyzer analyzer_signals = self.ethphy.debug - self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, + self.analyzer = LiteScopeAnalyzer(analyzer_signals, depth = 256, clock_domain = "sys", csr_csv = "analyzer.csv"