From fb478537e7d45512567b9b35b5a69c536cb588b2 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 25 Mar 2020 12:40:02 +0100 Subject: [PATCH] phy/gmii: use a BUFG between eth_rx.clk and eth_rx.clk. This makes it Xilinx specific, but without it ISE simplifies this as a single signal (which is fine) but is not able to keep track of the "keep" attribute of both signals and fails applying the constraints. --- liteeth/phy/gmii.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/liteeth/phy/gmii.py b/liteeth/phy/gmii.py index ec42698..081183c 100644 --- a/liteeth/phy/gmii.py +++ b/liteeth/phy/gmii.py @@ -58,7 +58,10 @@ class LiteEthPHYGMIICRG(Module, AutoCSR): # MII: Use PHY clock_pads.tx as eth_tx_clk, do not drive clock_pads.gtx self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx")) if isinstance(mii_mode, int) and (mii_mode == 0): - self.comb += self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk) + self.specials += Instance("BUFG", + i_I = self.cd_eth_rx.clk, + o_O = self.cd_eth_tx.clk, + ) else: # XXX Xilinx specific, replace BUFGMUX with a generic clock buffer? self.specials += Instance("BUFGMUX",