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Merge pull request #149 from trabucayre/etherbone_hybrid 

core/__init__: LiteEthUDPIPCore, LiteEthIPCore: expose interface & endianness at LiteEthUDPIPCore constructor. LiteEthIPCore: don't hardcode interface, pass macaddr and endianness to LiteEthMAC
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enjoy-digital 2023-10-23 18:33:46 +02:00 committed by GitHub
parent 09d31b5af8 daf1a1ac63
commit fc190e8f7b
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1 changed files with 9 additions and 1 deletions
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liteeth/core/__init__.py
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@ -23,6 +23,8 @@ class LiteEthIPCore(Module, AutoCSR):
tx_cdc_buffered = True,
rx_cdc_depth = 32,
rx_cdc_buffered = True,
interface = "crossbar",
endianness = "big",
):
# Parameters.
# -----------
@ -33,7 +35,9 @@ class LiteEthIPCore(Module, AutoCSR):
self.submodules.mac = LiteEthMAC(
phy = phy,
dw = dw,
interface = "crossbar",
interface = interface,
endianness = endianness,
hw_mac = mac_address,
with_preamble_crc = True,
with_sys_datapath = with_sys_datapath,
tx_cdc_depth = tx_cdc_depth,
@ -83,6 +87,8 @@ class LiteEthUDPIPCore(LiteEthIPCore):
tx_cdc_buffered = True,
rx_cdc_depth = 32,
rx_cdc_buffered = True,
interface = "crossbar",
endianness = "big",
):
# Parameters.
# -----------
@ -98,6 +104,8 @@ class LiteEthUDPIPCore(LiteEthIPCore):
arp_entries = arp_entries,
with_icmp = with_icmp,
dw = dw,
interface = interface,
endianness = endianness,
with_ip_broadcast = with_ip_broadcast,
with_sys_datapath = with_sys_datapath,
tx_cdc_depth = tx_cdc_depth,