From a696ccddb4dcf5635955d8456a67bc9d1fcf6ff5 Mon Sep 17 00:00:00 2001 From: Xiretza Date: Mon, 10 Feb 2020 11:01:31 +0100 Subject: [PATCH 1/5] Expose interrupt pin for standalone design --- liteeth/gen.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/liteeth/gen.py b/liteeth/gen.py index 9c604e9..ac9621f 100644 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -46,6 +46,8 @@ _io = [ ("sys_clock", 0, Pins(1)), ("sys_reset", 1, Pins(1)), + ("interrupt", 0, Pins(1)), + # MII PHY Pads ("mii_eth_clocks", 0, Subsignal("tx", Pins(1)), @@ -223,6 +225,8 @@ class MACCore(PHYCore): self.submodules += bridge self.add_wb_master(bridge.wishbone) + self.comb += self.platform.request("interrupt").eq(self.ethmac.ev.irq) + # UDP Core ----------------------------------------------------------------------------------------- class UDPCore(PHYCore): From 42a7b6c69db4ac28aaf90487e07d80e9c095da97 Mon Sep 17 00:00:00 2001 From: Xiretza Date: Mon, 10 Feb 2020 11:05:07 +0100 Subject: [PATCH 2/5] Allow little-endian interface for standalone design --- liteeth/gen.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/liteeth/gen.py b/liteeth/gen.py index ac9621f..4de1868 100644 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -208,10 +208,10 @@ class MACCore(PHYCore): } mem_map.update(SoCCore.mem_map) - def __init__(self, phy, clk_freq): + def __init__(self, phy, clk_freq, endianness): PHYCore.__init__(self, phy, clk_freq) - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") + self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") @@ -279,12 +279,13 @@ def main(): soc_core_args(parser) parser.add_argument("--phy", default="mii", help="Ethernet PHY(mii/rmii/gmii/rgmii)") parser.add_argument("--core", default="wishbone", help="Ethernet Core(wishbone/udp)") + parser.add_argument("--endianness", default="big", choices=("big", "little"), help="Wishbone endianness") parser.add_argument("--mac_address", default=0x10e2d5000000, help="MAC address") parser.add_argument("--ip_address", default="192.168.1.50", help="IP address") args = parser.parse_args() if args.core == "wishbone": - soc = MACCore(phy=args.phy, clk_freq=int(100e6)) + soc = MACCore(phy=args.phy, clk_freq=int(100e6), endianness=args.endianness) elif args.core == "udp": soc = UDPCore(phy=args.phy, clk_freq=int(100e6), mac_address = args.mac_address, From ec9bc578f2c67ad30c2d8f0facc2ef745ae35861 Mon Sep 17 00:00:00 2001 From: Xiretza Date: Tue, 11 Feb 2020 16:11:14 +0100 Subject: [PATCH 3/5] Fix MII tx_en signal width in standalone generator --- liteeth/gen.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/liteeth/gen.py b/liteeth/gen.py index 4de1868..dcfff04 100644 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -60,7 +60,7 @@ _io = [ Subsignal("rx_dv", Pins(1)), Subsignal("rx_er", Pins(1)), Subsignal("rx_data", Pins(4)), - Subsignal("tx_en", Pins(4)), + Subsignal("tx_en", Pins(1)), Subsignal("tx_data", Pins(4)), Subsignal("col", Pins(1)), Subsignal("crs", Pins(1)) From 153c1606706dc7d8335e5b6ae670d2da66d34309 Mon Sep 17 00:00:00 2001 From: Xiretza Date: Tue, 11 Feb 2020 17:09:36 +0100 Subject: [PATCH 4/5] Prioritise overridden interrupts and memory regions --- liteeth/gen.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/liteeth/gen.py b/liteeth/gen.py index dcfff04..7a9af3b 100644 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -198,15 +198,15 @@ class PHYCore(SoCMini): # MAC Core ----------------------------------------------------------------------------------------- class MACCore(PHYCore): - interrupt_map = { + interrupt_map = SoCCore.interrupt_map + interrupt_map.update({ "ethmac": 2, - } - interrupt_map.update(SoCCore.interrupt_map) + }) - mem_map = { + mem_map = SoCCore.mem_map + mem_map.update({ "ethmac": 0x50000000 - } - mem_map.update(SoCCore.mem_map) + }) def __init__(self, phy, clk_freq, endianness): PHYCore.__init__(self, phy, clk_freq) From 5767dfcb6c80bda5577fc8dbdcffd6c4e4cfa689 Mon Sep 17 00:00:00 2001 From: Xiretza Date: Tue, 11 Feb 2020 19:20:48 +0100 Subject: [PATCH 5/5] Honour --output-dir argument in generator --- liteeth/gen.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/liteeth/gen.py b/liteeth/gen.py index 7a9af3b..ab9d296 100644 --- a/liteeth/gen.py +++ b/liteeth/gen.py @@ -20,6 +20,7 @@ TODO: identify limitations """ import argparse +import os from migen import * @@ -277,6 +278,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteEth standalone core generator") builder_args(parser) soc_core_args(parser) + parser.set_defaults(output_dir="build") parser.add_argument("--phy", default="mii", help="Ethernet PHY(mii/rmii/gmii/rgmii)") parser.add_argument("--core", default="wishbone", help="Ethernet Core(wishbone/udp)") parser.add_argument("--endianness", default="big", choices=("big", "little"), help="Wishbone endianness") @@ -293,7 +295,7 @@ def main(): port = 6000) else: raise ValueError - builder = Builder(soc, output_dir="build", compile_gateware=False, csr_csv="build/csr.csv") + builder = Builder(soc, output_dir=args.output_dir, compile_gateware=False, csr_csv=os.path.join(args.output_dir, "csr.csv")) builder.build(build_name="liteeth_core") if __name__ == "__main__":