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liteeth/phy: Add USP_GTH_2500BASEX support.

This commit is contained in:
Florent Kermarrec 2024-01-23 15:50:01 +01:00
parent 664a633d29
commit fec0e23eb1
3 changed files with 13 additions and 3 deletions
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1
liteeth/gen.py
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@ -284,6 +284,7 @@ class PHYCore(SoCMini):
liteeth_phys.KU_1000BASEX,
liteeth_phys.KU_2500BASEX,
liteeth_phys.USP_GTH_1000BASEX,
liteeth_phys.USP_GTH_2500BASEX,
liteeth_phys.USP_GTY_1000BASEX,
]:
ethphy_pads = platform.request("sgmii")

1
liteeth/phy/__init__.py
View File

@ -40,4 +40,5 @@ from liteeth.phy.k7_1000basex import K7_2500BASEX
from liteeth.phy.ku_1000basex import KU_1000BASEX
from liteeth.phy.ku_1000basex import KU_2500BASEX
from liteeth.phy.usp_gth_1000basex import USP_GTH_1000BASEX
from liteeth.phy.usp_gth_1000basex import USP_GTH_2500BASEX
from liteeth.phy.usp_gty_1000basex import USP_GTY_1000BASEX

14
liteeth/phy/usp_gth_1000basex.py
View File

@ -19,8 +19,9 @@ from liteeth.phy.pcs_1000basex import *
class USP_GTH_1000BASEX(LiteXModule):
# Configured for 200MHz or 156.25MHz transceiver reference clock
dw = 8
tx_clk_freq = 125e6
linerate = 1.25e9
rx_clk_freq = 125e6
tx_clk_freq = 125e6
def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e6, with_csr=True, rx_polarity=0, tx_polarity=0):
assert refclk_freq in [200e6, 156.25e6]
pcs = PCS(lsb_first=True)
@ -331,7 +332,7 @@ class USP_GTH_1000BASEX(LiteXModule):
p_RXOOB_CFG = 0b000000110,
p_RXOOB_CLK_CFG = "PMA",
p_RXOSCALRESET_TIME = 0b00011,
p_RXOUT_DIV = 4,
p_RXOUT_DIV = {1.25e9 : 4, 3.125e9 : 2}[self.linerate],
p_RXPCSRESET_TIME = 0b00011,
p_RXPHBEACON_CFG = 0b0000000000000000,
p_RXPHDLY_CFG = 0b0010000001110000,
@ -442,7 +443,7 @@ class USP_GTH_1000BASEX(LiteXModule):
p_TXFIFO_ADDR_CFG = "LOW",
p_TXGBOX_FIFO_INIT_RD_ADDR = 4,
p_TXGEARBOX_EN = "FALSE",
p_TXOUT_DIV = 4,
p_TXOUT_DIV = {1.25e9 : 4, 3.125e9 : 2}[self.linerate],
p_TXPCSRESET_TIME = 0b00011,
p_TXPHDLY_CFG0 = 0b0110000001110000,
p_TXPHDLY_CFG1 = 0b0000000000001111,
@ -919,3 +920,10 @@ class USP_GTH_1000BASEX(LiteXModule):
def add_csr(self):
self._reset = CSRStorage()
self.comb += self.reset.eq(self._reset.storage)
# USP_GTH_2500BASEX PHY ----------------------------------------------------------------------------
class USP_GTH_2500BASEX(USP_GTH_1000BASEX):
linerate = 3.125e9
rx_clk_freq = 312.5e6
tx_clk_freq = 312.5e6