0e3e645b44
test/test_mac_wishbone: Update with TX/RX slot changes.
2024-06-25 18:16:47 +02:00
4eec8419d0
test/test_model: Update EtherbonePacket.
2023-11-10 16:14:26 +01:00
b8745ff99a
gen.py: Add UDP raw mode
2023-07-10 17:18:45 +02:00
6f0c1b6a91
test_xgmii_phy: remove vcd dump of XGMII test
...
Removes a slightly inappropriately named VCD dump created by the XGMII
tests which may or may not have been a result of some frustration
during the test implementation. :)
Fixes: 8da0423f64
2021-11-21 19:28:26 +01:00
8da0423f64
Add XGMII PHY tests based on captured CSV XGMII bus data
...
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-11-18 19:40:21 +01:00
23ab5d2eb7
test_stream: allow premature stopping of the stream_collector
...
Support passing a stop_cond function which can cause the
stream_collector to exit on a user-defined condition.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-11-18 19:10:21 +01:00
e11dbe8391
Create a local version of litex.soc.interconnect.packet to ease development of LiteEth specific Packetizer/Depacketizer's features.
...
Also move test_stream/test_packet.
This allow keeping last_be (that will be replaced in the future) self-contained to LiteEth and will
also simplify the rework on Packetizer/Depacketizer in LiteX, application in LitePCIe and
future rework/application in LiteEth.
2021-10-25 11:05:46 +02:00
6204994bad
common: Define eth_min_frame_length, eth_fcs_length and arp_min_length and use them in core/mac/model.
2021-10-05 14:10:41 +02:00
6daff12f50
Fix "is not" literal SyntaxWarning
...
Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-02-16 21:57:53 +10:30
617400fe9e
test/test_etherbone: disable for now (hanging).
2020-12-17 19:06:11 +01:00
e270956d2d
test/test_model: fix test_etherbone.
2020-12-17 18:37:47 +01:00
53057121e7
examples: remove old examples and update README (new benches/examples will be added).
2020-11-23 12:54:09 +01:00
64b85e621e
add SPDX License identifier to header and specify file is part or LiteEth.
...
Artix7/Ultrascale 1000BaseX is reused from MiSoC/LiteEthMini, specify it.
2020-08-23 16:07:12 +02:00
1d76d02ea6
frontend: rename tty to stream (tty was too specific since modules can be used for any kind of data stream).
2020-07-13 10:08:50 +02:00
ddcbc33e63
test/test_gen: update
2020-02-12 11:17:38 +01:00
f2b3f7eeb1
test: update test_etherbone, use litex.gen.sim for all tests
2019-11-25 11:43:16 +01:00
c71e42972a
test: add test_examples (and remove test/Makefile)
2019-11-25 09:35:16 +01:00
10a911088c
test: rename test_liteeth_gen to test_gen and call gen.py instead of liteeth_gen
2019-11-25 08:53:40 +01:00
6cce8c3c34
test: add test_liteeth_gen
2019-11-24 11:23:13 +01:00
91f0f4ce80
test/model: improve presentation/readability
2019-11-23 15:17:22 +01:00
36c9951235
test: regroup model tests in test_model and run it with Travis-CI
2019-11-23 14:55:55 +01:00
bd1ead88d1
test: update for ci, for now disable test_etherbone since does not seem to finish
2019-11-23 00:14:19 +01:00
ad187d35f2
add CONTRIBUTORS file and add copyright header to all files
2019-06-24 11:43:10 +02:00
fd6d6c30ba
mac: update imports
2019-06-24 11:23:13 +02:00
94af3d63d9
README: update and rename example_designs to examples
2018-08-31 08:26:37 +02:00
79a6ba7709
replace litex.gen imports with migen imports
2018-02-23 13:40:09 +01:00
937c240727
test: fix test_model
2017-09-25 13:12:30 +02:00
ad9ecdbd5e
use udp port 1234 for etherbone
2017-06-22 11:28:45 +02:00
c4856d1eb5
test: start converting to python unittest
2017-01-19 14:33:24 +01:00
f55ce1aac6
core/mac: simplify/improve performance of LiteEthMACSRAMReader
...
now read data from sram on every clock cycle, allow lower system clock frequency (tested with 50MHz system clock / 125MHz ethernet clock)
2016-04-03 22:53:02 +02:00
e006223fee
test: fix model_tb
2016-03-31 00:25:50 +02:00
b394f2f45e
test/mac_wishbone_tb: fix simulation
2016-03-25 12:26:02 +01:00
b7f3b3ef42
test: finish etherbone_tb (simulator limitation removed)
2016-03-23 09:48:02 +01:00
87924c84e6
test: finish mac_wishbone_tb (simulator limitation removed)
2016-03-23 09:47:47 +01:00
7ea1b5a22d
test: use passive generators and some cleanup
2016-03-23 01:42:35 +01:00
e73f35c733
test: remove __init__.py and use setup.py develop
2016-03-22 10:34:28 +01:00
2f15f3748e
test: use new simulator (still etherbone_tb and mac_wishbone_tb not working due to use of FullMemoryWE)
2016-03-21 19:59:29 +01:00
657ba4cb16
global: use valid/ready/last signals instead of stb/ack/eop (similar to AXI)
2016-03-16 21:36:07 +01:00
51f56e79dd
global: remove use of sop
2016-03-16 16:22:00 +01:00
32243934fb
global: use stream.Endpoint instead of Sink/Source (deprecated)
2016-03-15 16:50:00 +01:00
d38612db0c
remove use of Record.connect
2015-12-27 12:26:01 +01:00
f1725d5fd1
ethetbone software is now integrated in LiteX
2015-11-17 12:04:04 +01:00
e7caf8acfb
use stream_packet and stream_sim from litex
2015-11-14 00:42:33 +01:00
d84d610104
simulations working with litex and vpi
2015-11-13 15:11:57 +01:00
7b9dc92b0b
for now use our fork of migen
2015-11-13 14:48:53 +01:00
886108eee9
test: for now revert all simulation (we'll switch when missing feature of new simulator will be implemted)
2015-11-13 14:47:57 +01:00
57b70c640c
start adapting simulations to new migen (still some issues with Migen simulator)
...
Simulator issues:
- MultiReg not simulated correctly (I've used direct instantiation of MultiRegImpl to get simulation working)
- MemoryArray with granularity != 1 raise NotImplementedError
2015-11-13 13:46:05 +01:00
e33937f089
move etherbone packets and record description to software
2015-10-13 21:36:37 +02:00
b4c3223a24
update litescope and build Devel targets in test
2015-09-27 19:17:07 +02:00
d786380cd2
fix simulations (adapt to new organization) and and all target in Makefile to for regression testing
2015-09-12 20:53:14 +02:00
Florent Kermarrec
rowanG077
Leon Schuermann
Joel Stanley