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709 Commits

Author SHA1 Message Date
GustavsC ac70566ab4 Create v7_1000basex.py 
Adding Virtex 7 1000 Basex
 2024-09-17 11:24:38 -03:00
Florent Kermarrec b573e1267c phy/xgmii: Add Clk/Data Pads definition to avoid duplication in PHYs. 2024-09-16 11:35:33 +02:00
Florent Kermarrec 78513c2ba7 frontend/stream: Add 64-bit data_width support. 2024-09-12 18:46:11 +02:00
Florent Kermarrec b1f916a447 frontend/etherbone: Add LiteEthLastHandler to LiteEthEtherbonePacketRX for 64-bit data-width support. 2024-09-12 13:33:49 +02:00
Florent Kermarrec 0b5389feab mac: Move LiteEthMACLastBE module to common.py and rename to LiteEthLastHandler. 2024-09-12 13:32:38 +02:00
Florent Kermarrec a2a862dc1b liteeth_gen: Add XGMII PHY support (Transceiver still need to be integrated externally). 2024-09-11 15:21:24 +02:00
Gwenhael Goavec-Merou 74bd085757
Merge pull request #168 from trabucayre/efinix_rework_primitives 
Efinix rework primitives
 2024-09-10 18:41:06 +02:00
Gwenhael Goavec-Merou 9496fd229f phy/titaniumrgmii.py: uses ClockSignal for DDRInput/DDROutput/ClkOutput, added cd for eth_tx_delayed, removed name=xxx for clkout with a cd 2024-09-10 11:52:48 +02:00
Gwenhael Goavec-Merou 88387cbd11 phy/trionrgmii.py: use ClockSignal for ClkOutput 'o', remove name parameter when a cd is used 2024-09-10 11:27:47 +02:00
Gwenhael Goavec-Merou 577a47222c phy/trionrgmii.py: DDRInput/DDROutput switch clk to a ClockSignal 2024-09-10 08:09:03 +02:00
Gwenhael Goavec-Merou ea07f5c421 phy/titaniumrgmii,trionrgmii: fixed pll clkin name by appending a '0' to match ClkInput / get_pin_name modifications introduces by LiteX commit d3161ad74c4b2afd5635f76f566c37f362eb166a 2024-09-04 14:48:34 +02:00
Gwenhael Goavec-Merou ecaebfe645 phy/trionrgmii.py: fixed RX and TX sides. RX: forces phase align by usign it as PLL's feedback. TX: reduces PLL phase shift 90 -> 45 2024-09-03 15:08:09 +02:00
enjoy-digital 9780327251
Merge pull request #167 from VOGL-electronic/fix_liteethmac 
mac/__init__.py: Fix LiteEthMAC.
 2024-08-27 09:20:33 +02:00
Fin Maaß 7086f6d0ea
mac/__init__.py: Fix LiteEthMAC. 
This fixes LiteEthMAC and
LiteEthMACCoreCrossbar.

Its also renames the depacketizer in
LiteEthMACCoreCrossbar for mac filtering
to filter_depacketizer, so it is not mixed up
with self.depacketizer.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2024-08-27 08:41:26 +02:00
Florent Kermarrec edc7188faa mac/__init__.py: Improve/Cleanup LiteEthMAC. 2024-08-19 10:19:53 +02:00
Florent Kermarrec bfc07e543a mac/__init__: Add comments on RX broadcard/filtering and minor cleanups. 2024-08-19 09:58:53 +02:00
Florent Kermarrec 0bb6c53795 mac/__init__.py: Switch to LiteXModule and cosmetic improvements. 2024-08-19 09:38:35 +02:00
enjoy-digital 55bae6b7b4
Merge pull request #165 from VOGL-electronic/fix_packet_handling 
MAC: Implement address filtering for logic interface in hybrid mode
 2024-08-19 09:27:54 +02:00
enjoy-digital 9531af62a7
Merge pull request #166 from VOGL-electronic/fix_etherbone 
Fix etherbone reads
 2024-08-19 09:26:25 +02:00
Florent Kermarrec 964df3ac2f phy/a7_gtp: Add separators and remove __all__. 2024-08-19 09:24:34 +02:00
enjoy-digital c04ac8f698
Merge pull request #164 from VOGL-electronic/optional_liteiclink 
Only import liteiclink when required
 2024-08-19 09:17:01 +02:00
Florent Kermarrec d4fa6a2f4a phy/a7_gtp: Add additionnal comment to #163 and express delay in us. 2024-08-19 09:16:20 +02:00
enjoy-digital 32df4523ba
Merge pull request #163 from cyntem/patch-1 
Update a7_gtp.py  transceiver resets have to stay low for 10us.
 2024-08-19 09:14:05 +02:00
Matthias Breithaupt 7b4429e814 Fix etherbone reads 
Since https://github.com/enjoy-digital/litex/pull/1999, etherbone reads
might result in garbage being output. This is caused by `be` not being
set during the read.

Fixes https://github.com/enjoy-digital/litex/issues/2031

Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
 2024-08-18 17:20:05 +02:00
Matthias Breithaupt da6e053f78 mac: implement mac filtering for logic interface in hybrid mode 2024-07-22 12:57:44 +02:00
Matthias Breithaupt 85c3ab2c51 Only import liteiclink when required 
As liteiclink is only used in the phy implementations of a few Xilinx/AMD
FPGAs, it does not make sense that it would be required to build liteeth
for any FPGA.

Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
 2024-07-14 22:36:26 +02:00
cyntem 4653a09aec
Update a7_gtp.py 
After testing several boards with XC7A200T chips, I found, that SFP works well only with setting more than 10us. The most of the XC7A200T chips works with 500ns, but some boards need 10us.
 2024-07-14 20:05:00 +03:00
Florent Kermarrec 583137eaf3 phy/1000basex: Use pll.config["d"] to compute TX_PROGDIV_CFG/RX_PROGDIV_CFG to fix behavior with 200MHz ref_clk_freq. 2024-07-10 16:21:11 +02:00
Florent Kermarrec e0f053e7a2 bench: Set margin to 0 on 1000/2500BaseX reference clock generation. 2024-07-10 15:39:04 +02:00
Florent Kermarrec 08c10774b5 phy/xgmii: Switch to LiteXModule and some cleanups. 2024-07-10 11:56:08 +02:00
Florent Kermarrec ec7320f003 mac/wishbone: Fix ntxslots/nrxslots == 1 case. 
Previously, a common decoder was used for TX and RX slots, so there were at least
two interfaces connected. With the TX/RX decoupling, we now only have on interface
per decoder when ntxslots/nrxslots == 1.
 2024-07-02 13:50:06 +02:00
Florent Kermarrec a00640bf67 liteeth/mac/sram: Switch to LiteXModule. 2024-06-26 15:44:30 +02:00
enjoy-digital e4f5385ef1
Merge pull request #161 from enjoy-digital/wishbone_tx_rx_buses 
mac/wishbone/LiteEthMACWishboneInterface: Expose separate TX/RX Wishb…
 2024-06-25 19:04:38 +02:00
Florent Kermarrec a118dd146f liteeth/gen: Update MACCore with EthMAC changes. 2024-06-25 18:53:46 +02:00
Florent Kermarrec 80bded4ffc liteeth/mac/wishbone: Fix write_only mode on RX. 2024-06-25 18:26:20 +02:00
Florent Kermarrec ec05e9c35c liteeth/mac/wishbone: Update copyrights. 2024-06-25 18:17:02 +02:00
Florent Kermarrec 0e3e645b44 test/test_mac_wishbone: Update with TX/RX slot changes. 2024-06-25 18:16:47 +02:00
Florent Kermarrec 591b77e991 mac/wishbone: Switch to LiteXModule. 2024-06-25 17:57:16 +02:00
Florent Kermarrec 20e892c214 mac/wishbone: Add _expose_wishbone_sram_interfaces to avoid duplicating code between TX and RX. 2024-06-25 17:56:12 +02:00
Florent Kermarrec 151b421a2c mac/wishbone/LiteEthMACWishboneInterface: Expose separate TX/RX Wishbone buses to allow simultaneous TX/RX SRAM accesses. 
Useful in some designs to optimize throughput.
 2024-06-25 17:36:18 +02:00
Florent Kermarrec 7d24ac33ae version: Bump to 2024.04. 2024-06-05 22:07:12 +02:00
enjoy-digital e209a1c697
Merge pull request #160 from whiteb3ar/master 
phy/ecp5rgmii.py: In-Band Status CSRField("clock_speed") size fixed
 2024-04-14 08:26:23 +02:00
Andrei Novysh 0e8079a9da phy/ecp5rgmii.py: In-Band Status CSRField("clock_speed") size fixed 2024-04-14 00:37:31 +03:00
Florent Kermarrec a0d59dd264 frontend/stream/LiteEthStream2UDPTX: Condition source.last_be to source.last. 2024-04-11 10:47:02 +02:00
Florent Kermarrec 79ccffcfa7 mac/crc: Revert 30e66a7 (introducing a regression). 2024-04-08 17:51:53 +02:00
Florent Kermarrec 421e008fc8 mac/crc: Cosmetic cleanup. 2024-04-05 09:20:28 +02:00
Florent Kermarrec fb407ce98b core/ip/LiteEthIPTX: Enable buffer to ease timings on checksum. 2024-04-04 17:58:30 +02:00
Florent Kermarrec b5d7ba1220 core/udp: Revert TX/RX Buffer since not helping (at least for now). 2024-04-04 17:52:43 +02:00
Florent Kermarrec 211cdc26f3 core/ip: Add optional input buffer on LiteEthIPTX to improve timings. 2024-04-04 17:26:54 +02:00
Florent Kermarrec 30e66a7e21 mac/crc/LiteEthMACCRC32: Avoid multiple XORs/Checks on output. 2024-04-04 16:39:32 +02:00