118 lines
4.3 KiB
Markdown
118 lines
4.3 KiB
Markdown
```
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__ _ __ ______ __
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/ / (_) /____ / __/ /_/ /
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/ /__/ / __/ -_) _// __/ _ \
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/____/_/\__/\__/___/\__/_//_/
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Copyright 2012-2024 / EnjoyDigital
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A small footprint and configurable Ethernet core
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powered by Migen & LiteX
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```
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[](https://github.com/enjoy-digital/liteeth/actions) 
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[> Intro
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--------
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LiteEth provides a small footprint and configurable Ethernet core.
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LiteEth is part of LiteX libraries whose aims are to lower entry level of
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complex FPGA cores by providing simple, elegant and efficient implementations
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of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
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Using Migen to describe the HDL allows the core to be highly and easily configurable.
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LiteEth can be used as LiteX library or can be integrated with your standard
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design flow by generating the verilog rtl that you will use as a standard core.
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[> Features
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-----------
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PHY:
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- MII, RMII 100Mbps PHYs.
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- GMII / RGMII / SGMII / 1000BaseX 1Gbps PHYs.
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- SGMII / 2500BaseX 3.125Gbps PHYs.
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| - | All | ECP5 | Spartan6 | Trion | Titanium | 7-Series | Ultrascale(+) |
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|-------|-----|------|----------|-------|----------|----------|---------------|
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| MII | X | X | X | X | X | X | X |
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| RMII | X | X | X | X | X | X | X |
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| GMII | | | X | | | X | X |
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| RGMII | | X | X | X | X | X | X |
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| SGMII | | | | | | X | X |
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Core:
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- Configurable MAC (HW or SW interface)
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- ARP / ICMP / UDP (HW or SW) / DHCP
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Frontend:
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- Etherbone (Wishbone over UDP: Slave or Master support)
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- UDP Streaming.
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[> FPGA Proven
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---------------
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LiteEth is already used in commercial and open-source designs:
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- MiSoC: http://m-labs.hk/gateware.html
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- ARTIQ: http://m-labs.hk/artiq/index.html
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- HDMI2USB: http://hdmi2usb.tv/home/
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- and others commercial designs...
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[> Possible improvements
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------------------------
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- add standardized interfaces (AXI, Avalon-ST)
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- add DMA interface to MAC
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- add more documentation
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- ... See below Support and consulting :)
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If you want to support these features, please contact us at florent [AT]
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enjoy-digital.fr.
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[> Getting started
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------------------
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1. Install Python 3.6+ and FPGA vendor's development tools.
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2. Install LiteX and the cores by following the LiteX's wiki [installation guide](https://github.com/enjoy-digital/litex/wiki/Installation).
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3. You can find examples of integration of the core with LiteX in LiteX-Boards and in the examples directory.
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[> Tests
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--------
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Unit tests are available in ./test/.
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To run all the unit tests:
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```sh
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$ ./setup.py test
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```
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Tests can also be run individually:
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```sh
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$ python3 -m unittest test.test_name
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```
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[> License
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----------
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LiteEth is released under the very permissive two-clause BSD license. Under
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the terms of this license, you are authorized to use LiteEth for closed-source
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proprietary designs.
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Even though we do not require you to do so, those things are awesome, so please
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do them if possible:
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- tell us that you are using LiteEth
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- cite LiteEth in publications related to research it has helped
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- send us feedback and suggestions for improvements
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- send us bug reports when something goes wrong
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- send us the modifications and improvements you have done to LiteEth.
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[> Support and consulting
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-------------------------
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We love open-source hardware and like sharing our designs with others.
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LiteEth is developed and maintained by EnjoyDigital.
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If you would like to know more about LiteEth or if you are already a happy
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user and would like to extend it for your needs, EnjoyDigital can provide standard
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commercial support as well as consulting services.
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So feel free to contact us, we'd love to work with you! (and eventually shorten
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the list of the possible improvements :)
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[> Contact
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E-mail: florent [AT] enjoy-digital.fr |