66 lines
2.4 KiB
Python
66 lines
2.4 KiB
Python
# This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import unittest
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from migen import *
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.stream_sim import *
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from liteeth.common import *
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from liteeth.core import LiteEthUDPIPCore
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from test.model import phy, mac, arp, ip, udp
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ip_address = 0x12345678
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mac_address = 0x12345678abcd
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class DUT(Module):
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def __init__(self, dw=8):
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self.dw = dw
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self.submodules.phy_model = phy.PHY(8, debug=False)
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self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
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self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
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self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=False, loopback=False)
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self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=False, loopback=True)
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self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000)
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udp_port = self.core.udp.crossbar.get_port(0x5678, dw)
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self.submodules.streamer = PacketStreamer(eth_udp_user_description(dw))
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self.submodules.logger = PacketLogger(eth_udp_user_description(dw))
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self.comb += [
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Record.connect(self.streamer.source, udp_port.sink),
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udp_port.sink.ip_address.eq(0x12345678),
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udp_port.sink.src_port.eq(0x1234),
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udp_port.sink.dst_port.eq(0x5678),
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udp_port.sink.length.eq(64//(dw//8)),
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Record.connect(udp_port.source, self.logger.sink)
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]
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def main_generator(dut):
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packet = Packet([i for i in range(64//(dut.dw//8))])
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dut.streamer.send(packet)
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yield from dut.logger.receive()
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# check results
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s, l, e = check(packet, dut.logger.packet)
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print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
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class TestUDP(unittest.TestCase):
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def test(self):
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dut = DUT(8)
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generators = {
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"sys" : [main_generator(dut),
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dut.streamer.generator(),
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dut.logger.generator()],
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"eth_tx": [dut.phy_model.phy_sink.generator(),
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dut.phy_model.generator()],
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"eth_rx": dut.phy_model.phy_source.generator()
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}
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clocks = {"sys": 10,
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"eth_rx": 10,
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"eth_tx": 10}
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run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
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