52 lines
1.7 KiB
Python
52 lines
1.7 KiB
Python
import unittest
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from litex.gen import *
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.stream_sim import *
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from liteeth.common import *
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from liteeth.core.mac import LiteEthMAC
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from liteeth.core.arp import LiteEthARP
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from test.model import phy, mac, arp
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ip_address = 0x12345678
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mac_address = 0x12345678abcd
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class DUT(Module):
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def __init__(self):
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self.submodules.phy_model = phy.PHY(8, debug=False)
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self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
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self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
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self.submodules.mac = LiteEthMAC(self.phy_model, dw=8, with_preamble_crc=True)
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self.submodules.arp = LiteEthARP(self.mac, mac_address, ip_address, 100000)
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def main_generator(dut):
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while (yield dut.arp.table.request.ready) != 1:
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yield dut.arp.table.request.valid.eq(1)
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yield dut.arp.table.request.ip_address.eq(0x12345678)
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yield
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yield dut.arp.table.request.valid.eq(0)
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while (yield dut.arp.table.response.valid) != 1:
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yield dut.arp.table.response.ready.eq(1)
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yield
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print("Received MAC : 0x{:12x}".format((yield dut.arp.table.response.mac_address)))
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class TestARP(unittest.TestCase):
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def test(self):
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dut = DUT()
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generators = {
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"sys" : [main_generator(dut)],
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"eth_tx": [dut.phy_model.phy_sink.generator(),
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dut.phy_model.generator()],
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"eth_rx": dut.phy_model.phy_source.generator()
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}
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clocks = {"sys": 10,
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"eth_rx": 10,
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"eth_tx": 10}
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run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
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