151 lines
4.5 KiB
Python
151 lines
4.5 KiB
Python
import unittest
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from litex.gen import *
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.stream_sim import *
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from liteeth.common import *
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from liteeth.core.mac import LiteEthMAC
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from test.model import phy, mac
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class WishboneMaster:
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def __init__(self, obj):
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self.obj = obj
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self.dat = 0
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def write(self, adr, dat):
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yield self.obj.cyc.eq(1)
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yield self.obj.stb.eq(1)
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yield self.obj.adr.eq(adr)
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yield self.obj.we.eq(1)
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yield self.obj.sel.eq(0xf)
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yield self.obj.dat_w.eq(dat)
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while not (yield self.obj.ack):
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yield
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yield self.obj.cyc.eq(0)
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yield self.obj.stb.eq(0)
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yield
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def read(self, adr):
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yield self.obj.cyc.eq(1)
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yield self.obj.stb.eq(1)
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yield self.obj.adr.eq(adr)
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yield self.obj.we.eq(0)
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yield self.obj.sel.eq(0xf)
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yield self.obj.dat_w.eq(0)
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while not (yield self.obj.ack):
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yield
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self.dat = (yield self.obj.dat_r)
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yield self.obj.cyc.eq(0)
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yield self.obj.stb.eq(0)
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yield
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class SRAMReaderDriver:
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def __init__(self, obj):
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self.obj = obj
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def start(self, slot, length):
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yield self.obj._slot.storage.eq(slot)
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yield self.obj._length.storage.eq(length)
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yield self.obj._start.re.eq(1)
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yield
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yield self.obj._start.re.eq(0)
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yield
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def wait_done(self):
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while not (yield self.obj.ev.done.pending):
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yield
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def clear_done(self):
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yield self.obj.ev.pending.re.eq(1)
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yield self.obj.ev.pending.r.eq(1)
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yield
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yield self.obj.ev.pending.re.eq(0)
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yield self.obj.ev.pending.r.eq(0)
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yield
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class SRAMWriterDriver:
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def __init__(self, obj):
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self.obj = obj
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def wait_available(self):
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while not (yield self.obj.ev.available.pending):
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yield
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def clear_available(self):
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yield self.obj.ev.pending.re.eq(1)
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yield self.obj.ev.pending.r.eq(1)
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yield
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yield self.obj.ev.pending.re.eq(0)
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yield self.obj.ev.pending.r.eq(0)
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yield
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class DUT(Module):
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def __init__(self):
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self.submodules.phy_model = phy.PHY(8, debug=False)
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self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=True)
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self.submodules.ethmac = LiteEthMAC(phy=self.phy_model, dw=32, interface="wishbone", with_preamble_crc=True)
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def main_generator(dut):
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wishbone_master = WishboneMaster(dut.ethmac.bus)
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sram_reader_driver = SRAMReaderDriver(dut.ethmac.interface.sram.reader)
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sram_writer_driver = SRAMWriterDriver(dut.ethmac.interface.sram.writer)
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sram_writer_slots_offset = [0x000, 0x200]
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sram_reader_slots_offset = [0x400, 0x600]
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length = 150+2
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tx_payload = [seed_to_data(i, True) % 0xff for i in range(length)] + [0, 0, 0, 0]
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errors = 0
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for i in range(2):
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for slot in range(2):
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print("slot {}: ".format(slot), end="")
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# fill tx memory
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for i in range(length//4+1):
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dat = int.from_bytes(tx_payload[4*i:4*(i+1)], "big")
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yield from wishbone_master.write(sram_reader_slots_offset[slot]+i, dat)
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# send tx payload & wait
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yield from sram_reader_driver.start(slot, length)
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yield from sram_reader_driver.wait_done()
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yield from sram_reader_driver.clear_done()
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# wait rx
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yield from sram_writer_driver.wait_available()
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yield from sram_writer_driver.clear_available()
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# get rx payload (loopback on PHY Model)
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rx_payload = []
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for i in range(length//4+1):
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yield from wishbone_master.read(sram_writer_slots_offset[slot]+i)
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dat = wishbone_master.dat
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rx_payload += list(dat.to_bytes(4, byteorder='big'))
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# check results
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s, l, e = check(tx_payload[:length], rx_payload[:min(length, len(rx_payload))])
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print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
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class TestMACWishbone(unittest.TestCase):
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def test(self):
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dut = DUT()
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generators = {
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"sys" : main_generator(dut),
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"eth_tx": [dut.phy_model.phy_sink.generator(),
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dut.phy_model.generator()],
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"eth_rx": dut.phy_model.phy_source.generator()
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}
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clocks = {"sys": 20,
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"eth_rx": 8,
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"eth_tx": 8}
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run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
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