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examples: remove obsolete examples rename litescope_test to litescope_cli and add it as console script.

This commit is contained in:
Florent Kermarrec 2020-08-05 12:39:17 +02:00
parent a80c964075
commit 0182377a07
12 changed files with 10 additions and 612 deletions
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155
examples/fast_scope_arty.py
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@ -1,155 +0,0 @@
#!/usr/bin/env python3
# This file is Copyright (c) 2019 kees.jongenburger <kees.jongenburger@gmail.com>
# License: BSD
import sys
from migen import *
from litex.build.generic_platform import *
from litex.build.io import DifferentialInput, CRG
from litex.build.tools import write_to_file
from litex.boards.platforms import arty
from litex.soc.integration.soc_core import SoCCore
from litex.soc.cores.uart import UARTWishboneBridge
from litex.soc.cores.clock import *
from litex.soc.integration import export
from litescope import LiteScopeIO, LiteScopeAnalyzer
#
# Use the 8 input on the dual PMOD connector B as input
# Those are the fast and not so well protected pins.
_serdes_io = [
("serdes_io", 0,
Subsignal("d0", Pins("E15"),IOStandard("LVCMOS33")),
Subsignal("d1", Pins("E16"),IOStandard("LVCMOS33")),
Subsignal("d2", Pins("D15"),IOStandard("LVCMOS33")),
Subsignal("d3", Pins("C15"),IOStandard("LVCMOS33")),
Subsignal("d4", Pins("J17"),IOStandard("LVCMOS33")),
Subsignal("d5", Pins("J18"),IOStandard("LVCMOS33")),
Subsignal("d6", Pins("K15"),IOStandard("LVCMOS33")),
Subsignal("d7", Pins("J15"),IOStandard("LVCMOS33")),
)
]
class SerdesInputSignal(Module):
def __init__(self, pad):
self.signals = Signal(8)
#
# Based on a 100MHz input clock and a 400MHz sample clock and
# Measuring at ddr speed we are sampling at 800Mhz
#
self.specials += Instance("ISERDESE2",
p_DATA_WIDTH=8, p_DATA_RATE="DDR",
p_SERDES_MODE="MASTER", p_INTERFACE_TYPE="NETWORKING",
p_NUM_CE=1, p_IOBDELAY="NONE",
i_D=pad,
i_CE1=1,
i_RST=ResetSignal("sys"),
i_CLK=ClockSignal("sys4x"), i_CLKB=~ClockSignal("sys4x"),
i_CLKDIV=ClockSignal("sys"),
i_BITSLIP=0,
o_Q8=self.signals[0], o_Q7=self.signals[1],
o_Q6=self.signals[2], o_Q5=self.signals[3],
o_Q4=self.signals[4], o_Q3=self.signals[5],
o_Q2=self.signals[6], o_Q1=self.signals[7]
)
class SerdesIO(Module):
def __init__(self,platform):
platform.add_extension(_serdes_io)
pads = platform.request("serdes_io")
self.submodules.d0 = SerdesInputSignal(pads.d0)
self.submodules.d1 = SerdesInputSignal(pads.d1)
self.submodules.d2 = SerdesInputSignal(pads.d2)
self.submodules.d3 = SerdesInputSignal(pads.d3)
self.submodules.d4 = SerdesInputSignal(pads.d4)
self.submodules.d5 = SerdesInputSignal(pads.d5)
self.submodules.d6 = SerdesInputSignal(pads.d6)
self.submodules.d7 = SerdesInputSignal(pads.d7)
platform.add_platform_command("""
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
""")
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
class LiteScopeSoC(SoCCore):
csr_map = {
"analyzer": 17
}
csr_map.update(SoCCore.csr_map)
def __init__(self, platform):
sys_clk_freq = int(100e6)
SoCCore.__init__(self, platform, sys_clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Fast scope", ident_version=True,
with_timer=False
)
self.submodules.serdes = SerdesIO(platform)
# crg
self.submodules.crg = _CRG(platform,sys_clk_freq)
# bridge
bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=115200)
self.submodules.bridge = bridge
self.add_wb_master(bridge.wishbone)
# Litescope Analyzer
analyzer_groups = {}
# Analyzer group
analyzer_groups[0] = [
self.serdes.d0.signals,
self.serdes.d1.signals,
self.serdes.d2.signals,
self.serdes.d3.signals,
]
# analyzer
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 512)
def do_exit(self, vns):
self.analyzer.export_csv(vns, "test/analyzer.csv")
platform = arty.Platform()
soc = LiteScopeSoC(platform)
vns = platform.build(soc, run="no-compile" not in sys.argv[1:])
#
# Create csr and analyzer files
#
soc.finalize()
csr_csv = export.get_csr_csv(soc.csr_regions, soc.constants)
write_to_file("test/csr.csv", csr_csv)
soc.do_exit(vns)

178
examples/make.py
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@ -1,178 +0,0 @@
#!/usr/bin/env python3
# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
import sys
import os
import argparse
import subprocess
import struct
import importlib
from migen.fhdl import verilog
from migen.fhdl.structure import _Fragment
from litex.build.tools import write_to_file
from litex.build.xilinx.common import *
from litex.soc.integration import export
def autotype(s):
if s == "True":
return True
elif s == "False":
return False
try:
return int(s, 0)
except ValueError:
pass
return s
def _import(default, name):
return importlib.import_module(default + "." + name)
def _get_args():
parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
description="""\
LiteScope - based on Migen & LiteX.
This program builds and/or loads LiteScope components.
One or several actions can be specified:
clean delete previous build(s).
build-core build verilog core.
build-bitstream build-bitstream build FPGA bitstream.
build-csr-csv save CSR map into CSV file.
load-bitstream load bitstream into volatile storage.
all clean, build-csr-csv, build-bitstream, load-bitstream.
""")
parser.add_argument("-t", "--target", default="simple", help="Core type to build")
parser.add_argument("-s", "--sub-target", default="", help="variant of the Core type to build")
parser.add_argument("-p", "--platform", default=None, help="platform to build for")
parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option")
parser.add_argument("-Op", "--platform-option", default=[], nargs=2, action="append", help="set platform-specific option")
parser.add_argument("-Ob", "--build-option", default=[], nargs=2, action="append", help="set build option")
parser.add_argument("--csr_csv", default="./test/csr.csv", help="CSV file to save the CSR map into")
parser.add_argument("action", nargs="+", help="specify an action")
return parser.parse_args()
if __name__ == "__main__":
args = _get_args()
# create top-level Core object
target_module = _import("targets", args.target)
if args.sub_target:
top_class = getattr(target_module, args.sub_target)
else:
top_class = target_module.default_subtarget
if hasattr(top_class, "platform"):
platform = top_class.platform
platform_name = top_class.platform.name
else:
if args.platform is None:
if hasattr(top_class, "default_platform"):
platform_name = top_class.default_platform
else:
raise ValueError("Target has no default platform, specify a platform with -p your_platform")
else:
platform_name = args.platform
try:
platform_module = _import("litex.boards.platforms", platform_name)
except:
platform_module = _import("migen.build.platforms", platform_name)
platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
platform = platform_module.Platform(**platform_kwargs)
build_name = top_class.__name__.lower() + "_" + platform_name
top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
soc = top_class(platform, **top_kwargs)
soc.finalize()
# decode actions
action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"]
actions = {k: False for k in action_list}
for action in args.action:
if action in actions:
actions[action] = True
else:
print("Unknown action: "+action+". Valid actions are:")
for a in action_list:
print(" "+a)
sys.exit(1)
print("""
__ _ __ ____
/ / (_) /____ / __/______ ___ ___
/ /__/ / __/ -_)\ \/ __/ _ \/ _ \/ -_)
/____/_/\__/\__/___/\__/\___/ .__/\__/
/_/
A small footprint and configurable embedded FPGA
logic analyzer core powered by Migen & LiteX
====== Building parameters: ======""")
if hasattr(soc, "io"):
print("""
LiteScopeIO
-----------
Width: {}
""".format(soc.io.data_width)
)
if hasattr(soc, "analyzer"):
print("""
LiteScopeAnalyzer
-----------------
Width: {}
Depth: {}
===============================""".format(
soc.analyzer.data_width,
soc.analyzer.depth
)
)
# dependencies
if actions["all"]:
actions["build-csr-csv"] = True
actions["build-bitstream"] = True
actions["load-bitstream"] = True
if actions["build-bitstream"]:
actions["build-csr-csv"] = True
if actions["clean"]:
subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-csv"]:
csr_csv = export.get_csr_csv(soc.csr_regions, soc.constants)
write_to_file(args.csr_csv, csr_csv)
if actions["build-core"]:
soc_fragment = soc.get_fragment()
platform.finalize(soc_fragment)
v_output = platform.get_verilog(soc_fragment, name="litescope",
special_overrides=xilinx_special_overrides)
if not os.path.exists("build"):
os.makedirs("build")
v_output.write("build/litescope.v")
if actions["build-bitstream"]:
build_kwargs = dict((k, autotype(v)) for k, v in args.build_option)
vns = platform.build(soc, build_name=build_name, **build_kwargs)
if hasattr(soc, "do_exit") and vns is not None:
if hasattr(soc.do_exit, '__call__'):
soc.do_exit(vns)
if actions["load-bitstream"]:
prog = platform.create_programmer()
prog.load_bitstream("build/" + build_name + platform.bitstream_ext)

0
examples/targets/__init__.py
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49
examples/targets/core.py
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@ -1,49 +0,0 @@
# This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from migen import *
from targets import *
from litex.build.generic_platform import *
from litex.build.xilinx.platform import XilinxPlatform
from litex.soc.integration.soc_core import SoCMini
from litescope import LiteScopeAnalyzer
_io = [
("sys_clock", 0, Pins(1)),
("sys_reset", 1, Pins(1)),
("serial", 0,
Subsignal("tx", Pins(1)),
Subsignal("rx", Pins(1)),
),
("bus", 0, Pins(128))
]
class CorePlatform(XilinxPlatform):
name = "core"
def __init__(self):
XilinxPlatform.__init__(self, "", _io)
class Core(SoCMini):
platform = CorePlatform()
def __init__(self, platform, clk_freq=100*1000000):
self.clock_domains.cd_sys = ClockDomain("sys")
self.comb += [
self.cd_sys.clk.eq(platform.request("sys_clock")),
self.cd_sys.rst.eq(platform.request("sys_reset"))
]
SoCMini.__init__(self, platform, clk_freq, csr_data_width=32,
with_uart=True, uart_name="bridge",
ident="Litescope example design", ident_version=True,
)
self.submodules.analyzer = LiteScopeAnalyzer(platform.request("bus"), 512)
self.add_csr("analyzer")
default_subtarget = Core

76
examples/targets/simple.py
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@ -1,76 +0,0 @@
# This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from migen import *
from litex.build.io import CRG
from litex.soc.integration.soc_core import SoCMini
from litescope import LiteScopeIO, LiteScopeAnalyzer
# LiteScope SoC ------------------------------------------------------------------------------------
class LiteScopeSoC(SoCMini):
def __init__(self, platform):
sys_clk_freq = int((1e9/platform.default_clk_period))
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self, platform, sys_clk_freq,
csr_data_width = 32,
with_uart = True,
uart_name = "bridge",
ident = "Litescope example design",
ident_version = True,
)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# Litescope IO -----------------------------------------------------------------------------
self.submodules.io = LiteScopeIO(8)
self.add_csr("io")
for i in range(8):
try:
self.comb += platform.request("user_led", i).eq(self.io.output[i])
except:
pass
# Litescope Analyzer -----------------------------------------------------------------------
analyzer_groups = {}
# Counter group
counter = Signal(16, name_override="counter")
zero = Signal(name_override="zero")
self.sync += counter.eq(counter + 1)
self.comb += zero.eq(counter == 0)
analyzer_groups[0] = [
zero,
counter,
]
# Communication group
analyzer_groups[1] = [
platform.lookup_request("serial").tx,
platform.lookup_request("serial").rx,
self.bus.masters["uartbone"],
]
# FSM group
fsm = FSM(reset_state="STATE1")
self.submodules += fsm
fsm.act("STATE1",
NextState("STATE2")
)
fsm.act("STATE2",
NextState("STATE1")
)
analyzer_groups[2] = [
fsm,
]
# Analyzer
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 512, csr_csv="test/analyzer.csv")
self.add_csr("analyzer")
default_subtarget = LiteScopeSoC

26
examples/test/test_analyzer_counter.py
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@ -1,26 +0,0 @@
#!/usr/bin/env python3
# This file is Copyright (c) 2018 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from litex import RemoteClient
from litescope import LiteScopeAnalyzerDriver
wb = RemoteClient()
wb.open()
# # #
analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True)
analyzer.configure_subsampler(1)
analyzer.configure_group(0)
analyzer.add_rising_edge_trigger("zero")
analyzer.run(offset=32, length=128)
analyzer.wait_done()
analyzer.upload()
analyzer.save("dump.vcd")
# # #
wb.close()

27
examples/test/test_analyzer_wishbone.py
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@ -1,27 +0,0 @@
#!/usr/bin/env python3
# This file is Copyright (c) 2018 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from litex import RemoteClient
from litescope import LiteScopeAnalyzerDriver
wb = RemoteClient()
wb.open()
# # #
analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True)
analyzer.configure_subsampler(1)
analyzer.configure_group(1)
analyzer.add_rising_edge_trigger("uartwishbonebridge_wishbone_stb")
analyzer.add_rising_edge_trigger("uartwishbonebridge_wishbone_ack")
analyzer.run(offset=32, length=128)
analyzer.wait_done()
analyzer.upload()
analyzer.save("dump.vcd")
# # #
wb.close()

30
examples/test/test_fast_scope_arty.py
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@ -1,30 +0,0 @@
#!/usr/bin/env python3
# This file is Copyright (c) 2019 kees.jongenburger <kees.jongenburger@gmail.com>
# License: BSD
from litex import RemoteClient
from litescope import LiteScopeAnalyzerDriver
wb = RemoteClient()
wb.open()
# # #
subsample = 1
analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True)
analyzer.configure_subsampler(subsample)
analyzer.configure_group(0)
analyzer.run(offset=32, length=512)
analyzer.wait_done()
analyzer.upload()
#
# Convert parallel input back to a flaten view (e.g. the 8 bits values are flattened)
#
analyzer.save("dump.vcd",flatten=True)
# # #
wb.close()

23
examples/test/test_identifier.py
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@ -1,23 +0,0 @@
#!/usr/bin/env python3
# This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
fpga_id = ""
for i in range(256):
c = chr(wb.read(wb.bases.identifier_mem + 4*i) & 0xff)
fpga_id += c
if c == "\0":
break
print(fpga_id)
# # #
wb.close()

47
examples/test/test_io.py
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@ -1,47 +0,0 @@
#!/usr/bin/env python3
# This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
import time
from litex import RemoteClient
from litescope import LiteScopeIODriver
wb = RemoteClient()
wb.open()
# # #
def led_anim0(inout):
for i in range(10):
io.write(0xa5)
time.sleep(0.1)
io.write(0x5a)
time.sleep(0.1)
def led_anim1(inout):
for j in range(4):
# Led <<
led_data = 1
for i in range(8):
io.write(led_data)
time.sleep(i*i*0.0020)
led_data = (led_data << 1)
# Led >>
ledData = 128
for i in range(8):
io.write(led_data)
time.sleep(i*i*0.0020)
led_data = (led_data >> 1)
io = LiteScopeIODriver(wb.regs, "io")
led_anim0(io)
led_anim1(io)
print("{:02x}".format(io.read()))
# # #
wb.close()

6
examples/test/test_litescope.py → litescope/software/litescope_cli.py
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@ -1,6 +1,7 @@
#!/usr/bin/env python3
# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
import re
@ -88,7 +89,7 @@ def add_triggers(args, analyzer, signals):
added = True
return added
if __name__ == "__main__":
def main():
args = parse_args()
signals = get_signals("analyzer.csv")
@ -113,3 +114,6 @@ if __name__ == "__main__":
analyzer.save("dump.vcd")
finally:
wb.close()
if __name__ == "__main__":
main()

5
setup.py
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@ -16,4 +16,9 @@ setup(
python_requires="~=3.6",
packages=find_packages(exclude=("test*", "sim*", "doc*", "examples*")),
include_package_data=True,
entry_points={
"console_scripts": [
"litescope_cli=litescope.software.litescope_cli:main",
],
},
)