From 01eabb2d0df62b5f9415bb62475d231da2a2204f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 22 Jun 2017 17:56:06 +0200 Subject: [PATCH] example_design: update with litex and fix --- example_designs/make.py | 5 +++-- example_designs/targets/simple.py | 2 -- example_designs/test/test_regs.py | 12 +++++++----- 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/example_designs/make.py b/example_designs/make.py index 0c1335d..eb60eaf 100644 --- a/example_designs/make.py +++ b/example_designs/make.py @@ -94,6 +94,7 @@ if __name__ == "__main__": try: memory_regions = soc.get_memory_regions() csr_regions = soc.get_csr_regions() + csr_constants = soc.get_constants() except: pass @@ -117,7 +118,7 @@ if __name__ == "__main__": /_/ A small footprint and configurable embedded FPGA - logic analyzer core powered by Migen + logic analyzer core powered by LiteX ====== Building parameters: ======""") if hasattr(soc, "io"): @@ -153,7 +154,7 @@ Depth: {} subprocess.call(["rm", "-rf", "build/*"]) if actions["build-csr-csv"]: - csr_csv = cpu_interface.get_csr_csv(csr_regions) + csr_csv = cpu_interface.get_csr_csv(csr_regions, csr_constants) write_to_file(args.csr_csv, csr_csv) if actions["build-core"]: diff --git a/example_designs/targets/simple.py b/example_designs/targets/simple.py index 43a71c2..f3cedd8 100644 --- a/example_designs/targets/simple.py +++ b/example_designs/targets/simple.py @@ -36,8 +36,6 @@ class LiteScopeSoC(SoCCore): counter = Signal(16) self.sync += counter.eq(counter + 1) - toto = Signal() - self.submodules.analyzer = LiteScopeAnalyzer(counter, 512) def do_exit(self, vns): diff --git a/example_designs/test/test_regs.py b/example_designs/test/test_regs.py index 822a232..1c790df 100644 --- a/example_designs/test/test_regs.py +++ b/example_designs/test/test_regs.py @@ -5,11 +5,13 @@ wb.open() # # # -identifier = "" -for i in range(30): - identifier += chr(wb.read(wb.bases.identifier_mem + 4*(i+1))) # TODO: why + 1? -print(identifier) -print("frequency : {}MHz".format(wb.constants.system_clock_frequency/1000000)) +fpga_id = "" +for i in range(256): + c = chr(wb.read(wb.bases.identifier_mem + 4*i) & 0xff) + fpga_id += c + if c == "\0": + break +print(fpga_id) # # #