diff --git a/examples/targets/core.py b/examples/targets/core.py
index a3747e7..41a4441 100644
--- a/examples/targets/core.py
+++ b/examples/targets/core.py
@@ -56,7 +56,7 @@ class Core(SoCCore):
             with_timer=False
         )
         self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
-        self.add_wb_master(self.cpu_or_bridge.wishbone)
+        self.add_wb_master(self.cpu.wishbone)
 
         self.bus = platform.request("bus")
         self.submodules.analyzer = LiteScopeAnalyzer((self.bus), 512)
diff --git a/examples/targets/simple.py b/examples/targets/simple.py
index a947a49..c01179d 100644
--- a/examples/targets/simple.py
+++ b/examples/targets/simple.py
@@ -32,7 +32,7 @@ class LiteScopeSoC(SoCCore):
         # bridge
         self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"),
             sys_clk_freq, baudrate=115200))
-        self.add_wb_master(self.cpu_or_bridge.wishbone)
+        self.add_wb_master(self.cpu.wishbone)
 
         # Litescope IO
         self.submodules.io = LiteScopeIO(8)