core: minor fixes

This commit is contained in:
Florent Kermarrec 2016-04-03 18:26:50 +02:00
parent 0f7f384ac9
commit 0c41c6a204
2 changed files with 12 additions and 8 deletions

View File

@ -134,13 +134,14 @@ class AnalyzerStorage(Module, AutoCSR):
If(self.sink.valid & self.sink.hit, If(self.sink.valid & self.sink.hit,
NextState("RUN") NextState("RUN")
), ),
mem.source.ready.eq(mem.level == self.offset.storage) mem.source.ready.eq(mem.level >= self.offset.storage)
) )
fsm.act("RUN", fsm.act("RUN",
self.run.status.eq(1), self.run.status.eq(1),
self.sink.connect(mem.sink, leave_out=set(["hit"])), self.sink.connect(mem.sink, leave_out=set(["hit"])),
If(~mem.sink.ready | (mem.level == self.length.storage), If(~mem.sink.ready | (mem.level >= self.length.storage),
NextState("IDLE") NextState("IDLE"),
mem.source.ready.eq(1)
) )
) )
self.comb += [ self.comb += [

View File

@ -8,15 +8,15 @@ class TB(Module):
counter = Signal(16) counter = Signal(16)
self.sync += counter.eq(counter + 1) self.sync += counter.eq(counter + 1)
self.submodules.analyzer = LiteScopeAnalyzer(counter, 128) self.submodules.analyzer = LiteScopeAnalyzer(counter, 512)
def main_generator(dut): def main_generator(dut):
yield dut.analyzer.frontend.trigger.value.storage.eq(0x0080) yield dut.analyzer.frontend.trigger.value.storage.eq(0x0080)
yield dut.analyzer.frontend.trigger.mask.storage.eq(0xfff0) yield dut.analyzer.frontend.trigger.mask.storage.eq(0xfff0)
yield dut.analyzer.frontend.subsampler.value.storage.eq(0) yield dut.analyzer.frontend.subsampler.value.storage.eq(2)
yield yield
yield dut.analyzer.storage.length.storage.eq(64) yield dut.analyzer.storage.length.storage.eq(256)
yield dut.analyzer.storage.offset.storage.eq(32) yield dut.analyzer.storage.offset.storage.eq(8)
for i in range(16): for i in range(16):
yield yield
yield dut.analyzer.storage.start.re.eq(1) yield dut.analyzer.storage.start.re.eq(1)
@ -31,9 +31,12 @@ def main_generator(dut):
yield dut.analyzer.storage.mem_ready.re.eq(1) yield dut.analyzer.storage.mem_ready.re.eq(1)
yield dut.analyzer.storage.mem_ready.r.eq(1) yield dut.analyzer.storage.mem_ready.r.eq(1)
yield yield
yield dut.analyzer.storage.mem_ready.re.eq(0)
yield dut.analyzer.storage.mem_ready.r.eq(0)
yield
print(data) print(data)
print(len(data)) print(len(data))
print(data[32])
if __name__ == "__main__": if __name__ == "__main__":
tb = TB() tb = TB()