core: minor fixes
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0f7f384ac9
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0c41c6a204
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@ -134,13 +134,14 @@ class AnalyzerStorage(Module, AutoCSR):
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If(self.sink.valid & self.sink.hit,
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NextState("RUN")
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),
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mem.source.ready.eq(mem.level == self.offset.storage)
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mem.source.ready.eq(mem.level >= self.offset.storage)
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)
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fsm.act("RUN",
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self.run.status.eq(1),
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self.sink.connect(mem.sink, leave_out=set(["hit"])),
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If(~mem.sink.ready | (mem.level == self.length.storage),
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NextState("IDLE")
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If(~mem.sink.ready | (mem.level >= self.length.storage),
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NextState("IDLE"),
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mem.source.ready.eq(1)
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)
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)
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self.comb += [
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@ -8,15 +8,15 @@ class TB(Module):
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counter = Signal(16)
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self.sync += counter.eq(counter + 1)
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self.submodules.analyzer = LiteScopeAnalyzer(counter, 128)
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self.submodules.analyzer = LiteScopeAnalyzer(counter, 512)
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def main_generator(dut):
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yield dut.analyzer.frontend.trigger.value.storage.eq(0x0080)
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yield dut.analyzer.frontend.trigger.mask.storage.eq(0xfff0)
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yield dut.analyzer.frontend.subsampler.value.storage.eq(0)
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yield dut.analyzer.frontend.subsampler.value.storage.eq(2)
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yield
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yield dut.analyzer.storage.length.storage.eq(64)
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yield dut.analyzer.storage.offset.storage.eq(32)
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yield dut.analyzer.storage.length.storage.eq(256)
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yield dut.analyzer.storage.offset.storage.eq(8)
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for i in range(16):
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yield
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yield dut.analyzer.storage.start.re.eq(1)
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@ -31,9 +31,12 @@ def main_generator(dut):
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yield dut.analyzer.storage.mem_ready.re.eq(1)
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yield dut.analyzer.storage.mem_ready.r.eq(1)
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yield
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yield dut.analyzer.storage.mem_ready.re.eq(0)
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yield dut.analyzer.storage.mem_ready.r.eq(0)
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yield
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print(data)
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print(len(data))
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print(data[32])
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if __name__ == "__main__":
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tb = TB()
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