From 13813457d74152e8c21f899508636ca374897500 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 14 Mar 2022 09:53:42 +0100 Subject: [PATCH] core/_Storage: Simplify/Fix w_conv.sink.data assignement. - Constant(0, pads_bits) breaks cases where pads_bits==0. - Assignement of MSBs to 0 is implicit. --- litescope/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litescope/core.py b/litescope/core.py index 1ae3f63..922f50e 100644 --- a/litescope/core.py +++ b/litescope/core.py @@ -227,7 +227,7 @@ class _Storage(Module, AutoCSR): pad_bits = - data_width % read_width self.submodules.w_conv = w_conv = stream.Converter(data_width + pad_bits, read_width) self.comb += [ - self.w_conv.sink.data.eq(Cat(cdc.source.data, Constant(0, pad_bits))), + self.w_conv.sink.data.eq(cdc.source.data), self.w_conv.sink.valid.eq(cdc.source.valid), cdc.source.ready.eq(self.w_conv.sink.ready), ]