diff --git a/examples/fast_scope_arty.py b/examples/fast_scope_arty.py
index e53e6ac..32e7e5a 100755
--- a/examples/fast_scope_arty.py
+++ b/examples/fast_scope_arty.py
@@ -114,9 +114,9 @@ class LiteScopeSoC(SoCCore):
         self.submodules.crg = _CRG(platform,sys_clk_freq)
 
         # bridge
-        self.add_cpu(UARTWishboneBridge(platform.request("serial"),
-            sys_clk_freq, baudrate=115200))
-        self.add_wb_master(self.cpu.wishbone)
+        bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=115200)
+        self.submodules.bridge = bridge
+        self.add_wb_master(bridge.wishbone)
 
         # Litescope Analyzer
         analyzer_groups = {}
diff --git a/examples/make.py b/examples/make.py
index 9271813..a065021 100755
--- a/examples/make.py
+++ b/examples/make.py
@@ -97,12 +97,6 @@ if __name__ == "__main__":
     top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
     soc = top_class(platform, **top_kwargs)
     soc.finalize()
-    try:
-        memory_regions = soc.get_memory_regions()
-        csr_regions = soc.get_csr_regions()
-        csr_constants = soc.get_constants()
-    except:
-        pass
 
     # decode actions
     action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"]
@@ -160,7 +154,7 @@ Depth: {}
         subprocess.call(["rm", "-rf", "build/*"])
 
     if actions["build-csr-csv"]:
-        csr_csv = cpu_interface.get_csr_csv(csr_regions, csr_constants)
+        csr_csv = cpu_interface.get_csr_csv(soc.csr_regions, soc.constants)
         write_to_file(args.csr_csv, csr_csv)
 
     if actions["build-core"]:
diff --git a/examples/targets/core.py b/examples/targets/core.py
index 41a4441..f2356a3 100644
--- a/examples/targets/core.py
+++ b/examples/targets/core.py
@@ -55,8 +55,9 @@ class Core(SoCCore):
             ident="Litescope example design",
             with_timer=False
         )
-        self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
-        self.add_wb_master(self.cpu.wishbone)
+        bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
+        self.submodules.bridge = bridge
+        self.add_wb_master(bridge.wishbone)
 
         self.bus = platform.request("bus")
         self.submodules.analyzer = LiteScopeAnalyzer((self.bus), 512)
diff --git a/examples/targets/simple.py b/examples/targets/simple.py
index c01179d..ad7d83e 100644
--- a/examples/targets/simple.py
+++ b/examples/targets/simple.py
@@ -30,9 +30,9 @@ class LiteScopeSoC(SoCCore):
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 
         # bridge
-        self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"),
-            sys_clk_freq, baudrate=115200))
-        self.add_wb_master(self.cpu.wishbone)
+        bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=115200)
+        self.submodules.bridge = bridge
+        self.add_wb_master(bridge.wishbone)
 
         # Litescope IO
         self.submodules.io = LiteScopeIO(8)
@@ -59,7 +59,7 @@ class LiteScopeSoC(SoCCore):
         analyzer_groups[1] = [
             platform.lookup_request("serial").tx,
             platform.lookup_request("serial").rx,
-            self.cpu_or_bridge.wishbone
+            bridge.wishbone
         ]
 
         # fsm group