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Merge pull request #30 from antmicro/jboc/registered-inputs 

litescope/core: add option to register input signals to cut timings
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enjoy-digital 2021-08-25 13:23:59 +02:00 committed by GitHub
parent 405b912829 824985cdd3
commit 1596bff127
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1 changed files with 8 additions and 2 deletions
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10
litescope/core.py
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@ -226,7 +226,7 @@ class _Storage(Module, AutoCSR):
class LiteScopeAnalyzer(Module, AutoCSR): class LiteScopeAnalyzer(Module, AutoCSR):
def __init__(self, groups, depth, clock_domain="sys", trigger_depth=16, csr_csv="analyzer.csv"): def __init__(self, groups, depth, clock_domain="sys", trigger_depth=16, register=0, csr_csv="analyzer.csv"):
self.groups = groups = self.format_groups(groups) self.groups = groups = self.format_groups(groups)
self.depth = depth self.depth = depth
@ -242,10 +242,16 @@ class LiteScopeAnalyzer(Module, AutoCSR):
# Mux # Mux
self.submodules.mux = _Mux(data_width, len(groups)) self.submodules.mux = _Mux(data_width, len(groups))
sd = getattr(self.sync, clock_domain)
for i, signals in groups.items(): for i, signals in groups.items():
s = Cat(signals)
for _ in range(register):
s_d = Signal(len(s))
sd += s_d.eq(s)
s = s_d
self.comb += [ self.comb += [
self.mux.sinks[i].valid.eq(1), self.mux.sinks[i].valid.eq(1),
self.mux.sinks[i].data.eq(Cat(signals)) self.mux.sinks[i].data.eq(s)
] ]
# Frontend # Frontend