diff --git a/litescope/core.py b/litescope/core.py
index 8cfc8cd..fa3c698 100644
--- a/litescope/core.py
+++ b/litescope/core.py
@@ -80,7 +80,7 @@ class _Trigger(Module, AutoCSR):
         self.submodules += flush
         self.comb += [
             flush.wait.eq(~(~enable & enable_d)), # flush when disabling
-            hit.eq((sink.data & mem.source.mask) == mem.source.value),
+            hit.eq((sink.data & mem.source.mask) == (mem.source.value & mem.source.mask)),
             mem.source.ready.eq((enable & hit) | ~flush.done),
         ]
 
@@ -92,7 +92,6 @@ class _Trigger(Module, AutoCSR):
             source.hit.eq(done)
         ]
 
-
 class _SubSampler(Module, AutoCSR):
     def __init__(self, data_width):
         self.sink   = sink   = stream.Endpoint(core_layout(data_width))
diff --git a/litescope/software/driver/analyzer.py b/litescope/software/driver/analyzer.py
index 95ab7de..37979b4 100644
--- a/litescope/software/driver/analyzer.py
+++ b/litescope/software/driver/analyzer.py
@@ -80,7 +80,7 @@ class LiteScopeAnalyzerDriver:
         if cond is not None:
             for k, v in cond.items():
                 value |= getattr(self, k + "_o")*v
-                mask |= getattr(self, k + "_m")
+                mask  |= getattr(self, k + "_m")
         self.trigger_mem_mask.write(mask)
         self.trigger_mem_value.write(value)
         self.trigger_mem_write.write(1)