VCD: Add samplerate support to fix displayed timestamps
To use this, pass the samplerate kwarg to LiteScopeAnalyzer(). If using the sys domain, soc_obj.sys_clk_freq works.
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@ -48,6 +48,7 @@ class LiteScopeSoC(BaseSoC):
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
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depth = 1024,
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clock_domain = "sys",
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samplerate = self.sys_clk_freq,
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csr_csv = "analyzer.csv")
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self.add_csr("analyzer")
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@ -226,9 +226,10 @@ class _Storage(Module, AutoCSR):
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class LiteScopeAnalyzer(Module, AutoCSR):
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def __init__(self, groups, depth, clock_domain="sys", trigger_depth=16, register=False, csr_csv="analyzer.csv"):
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self.groups = groups = self.format_groups(groups)
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self.depth = depth
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def __init__(self, groups, depth, samplerate=1e-12, clock_domain="sys", trigger_depth=16, register=False, csr_csv="analyzer.csv"):
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self.groups = groups = self.format_groups(groups)
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self.depth = depth
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self.samplerate = samplerate
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self.data_width = data_width = max([sum([len(s) for s in g]) for g in groups.values()])
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@ -294,6 +295,7 @@ class LiteScopeAnalyzer(Module, AutoCSR):
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return ",".join(args) + "\n"
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r = format_line("config", "None", "data_width", str(self.data_width))
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r += format_line("config", "None", "depth", str(self.depth))
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r += format_line("config", "None", "samplerate", str(self.samplerate))
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for i, signals in self.groups.items():
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for s in signals:
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r += format_line("signal", str(i), vns.get_name(s), str(len(s)))
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@ -118,6 +118,7 @@ class LiteScopeAnalyzerDriver:
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self.add_trigger(value, mask, cond)
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def configure_subsampler(self, value):
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self.subsampling = value
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self.subsampler_value.write(value-1)
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def run(self, offset=0, length=None):
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@ -166,11 +167,13 @@ class LiteScopeAnalyzerDriver:
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return self.data
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def save(self, filename, samplerate=None, flatten=False):
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if samplerate is None:
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samplerate = self.samplerate / self.subsampling
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if self.debug:
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print("[writing to " + filename + "]...")
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name, ext = os.path.splitext(filename)
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if ext == ".vcd":
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dump = VCDDump()
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dump = VCDDump(samplerate=samplerate)
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elif ext == ".csv":
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dump = CSVDump()
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elif ext == ".py":
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@ -6,6 +6,7 @@
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from itertools import count
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import datetime
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import re
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from litescope.software.dump.common import Dump, dec2bin
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@ -19,14 +20,37 @@ def vcd_codes():
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code = codechars[r] + code
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yield code
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_si_prefix2exp = {
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"": 0,
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"m": -3,
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"u": -6,
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"n": -9,
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"p": -12,
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"f": -15,
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}
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def _timescale_str2num(timescale):
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match = re.fullmatch("(\d+)(\w{0,1})s", timescale)
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num = int(match.group(1))
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si_prefix = match.group(2)
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exp = _si_prefix2exp[si_prefix]
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return num * 10**exp, si_prefix
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class VCDDump(Dump):
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def __init__(self, dump=None, timescale="1ps", comment=""):
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def __init__(self, dump=None, samplerate=1e-12, timescale="1ps", comment=""):
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Dump.__init__(self)
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self.variables = [] if dump is None else dump.variables
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self.timescale = timescale
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self.comment = comment
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self.cnt = -1
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# rescale the timescale from the provided one to one where it is equal to the samplerate
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# this lets us output sequential change timestamps which helps with software like PulseView
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# that slow down if a much smaller timescale than necessary is used
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timescale_seconds, si_prefix = _timescale_str2num(timescale)
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# factor of 2 scale is because of 2x samples from fake clock
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self.count_timescale = int(1 / (timescale_seconds * samplerate * 2))
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self.timescale_unit_str = si_prefix + "s"
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def change(self):
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r = ""
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@ -65,14 +89,12 @@ class VCDDump(Dump):
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def generate_timescale(self):
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r = "$timescale "
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r += self.timescale
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r += str(self.count_timescale) + self.timescale_unit_str
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r += " $end\n"
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return r
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def generate_vars(self):
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r = "$scope "
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r += self.timescale
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r += " $end\n"
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r = "$scope dumped_signals $end\n"
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for v in self.variables:
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r += "$var wire "
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r += str(v.width)
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