From 2877ead735efc9ac2493e19ff7cff59e9ff9e548 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 25 Apr 2016 19:16:14 +0200 Subject: [PATCH] core: remove rounding to next ceil_pow2 (not useful) --- litescope/core.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/litescope/core.py b/litescope/core.py index 90c9e84..066523e 100644 --- a/litescope/core.py +++ b/litescope/core.py @@ -7,9 +7,6 @@ from litex.soc.interconnect.csr import * from litex.soc.cores.gpio import GPIOInOut from litex.soc.interconnect import stream -def ceil_pow2(v): - return 2**(bits_for(v-1)) - def core_layout(dw, hw=1): return [("data", dw), ("hit", hw)] @@ -166,7 +163,7 @@ class LiteScopeIO(Module, AutoCSR): class LiteScopeAnalyzer(Module, AutoCSR): def __init__(self, signals, depth, cd="sys", cd_ratio=1): self.signals = [signals] if not isinstance(signals, list) else signals - self.dw = ceil_pow2(sum([len(s) for s in signals])) + self.dw = sum([len(s) for s in signals]) self.core_dw = self.dw*cd_ratio self.depth = depth