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litescope
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core: remove rounding to next ceil_pow2 (not useful)

This commit is contained in:
Florent Kermarrec 2016-04-25 19:16:14 +02:00
parent 9eb97d7879
commit 2877ead735
1 changed files with 1 additions and 4 deletions
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5
litescope/core.py
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@ -7,9 +7,6 @@ from litex.soc.interconnect.csr import *
from litex.soc.cores.gpio import GPIOInOut from litex.soc.cores.gpio import GPIOInOut
from litex.soc.interconnect import stream from litex.soc.interconnect import stream
def ceil_pow2(v):
return 2**(bits_for(v-1))
def core_layout(dw, hw=1): def core_layout(dw, hw=1):
return [("data", dw), ("hit", hw)] return [("data", dw), ("hit", hw)]
@ -166,7 +163,7 @@ class LiteScopeIO(Module, AutoCSR):
class LiteScopeAnalyzer(Module, AutoCSR): class LiteScopeAnalyzer(Module, AutoCSR):
def __init__(self, signals, depth, cd="sys", cd_ratio=1): def __init__(self, signals, depth, cd="sys", cd_ratio=1):
self.signals = [signals] if not isinstance(signals, list) else signals self.signals = [signals] if not isinstance(signals, list) else signals
self.dw = ceil_pow2(sum([len(s) for s in signals])) self.dw = sum([len(s) for s in signals])
self.core_dw = self.dw*cd_ratio self.core_dw = self.dw*cd_ratio
self.depth = depth self.depth = depth