From 2f625c58b273c1913b81df7ce210c8f44038b7e7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 19 Apr 2017 10:46:17 +0200 Subject: [PATCH] update litex uart --- example_designs/targets/core.py | 2 +- example_designs/targets/simple.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/example_designs/targets/core.py b/example_designs/targets/core.py index aef6dca..b2506c9 100644 --- a/example_designs/targets/core.py +++ b/example_designs/targets/core.py @@ -7,7 +7,7 @@ from litex.build.generic_platform import * from litex.build.xilinx.platform import XilinxPlatform from litex.soc.integration.soc_core import SoCCore -from litex.soc.cores.uart.bridge import UARTWishboneBridge +from litex.soc.cores.uart import UARTWishboneBridge from litescope import LiteScopeAnalyzer diff --git a/example_designs/targets/simple.py b/example_designs/targets/simple.py index ff270ea..43a71c2 100644 --- a/example_designs/targets/simple.py +++ b/example_designs/targets/simple.py @@ -2,7 +2,7 @@ from litex.gen import * from litex.gen.genlib.io import CRG from litex.soc.integration.soc_core import SoCCore -from litex.soc.cores.uart.bridge import UARTWishboneBridge +from litex.soc.cores.uart import UARTWishboneBridge from litescope import LiteScopeIO, LiteScopeAnalyzer