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update litex uart

This commit is contained in:
Florent Kermarrec 2017-04-19 10:46:17 +02:00
parent f2d63aa1f3
commit 2f625c58b2
2 changed files with 2 additions and 2 deletions
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2
example_designs/targets/core.py
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@ -7,7 +7,7 @@ from litex.build.generic_platform import *
from litex.build.xilinx.platform import XilinxPlatform
from litex.soc.integration.soc_core import SoCCore
from litex.soc.cores.uart.bridge import UARTWishboneBridge
from litex.soc.cores.uart import UARTWishboneBridge
from litescope import LiteScopeAnalyzer

2
example_designs/targets/simple.py
View File

@ -2,7 +2,7 @@ from litex.gen import *
from litex.gen.genlib.io import CRG
from litex.soc.integration.soc_core import SoCCore
from litex.soc.cores.uart.bridge import UARTWishboneBridge
from litex.soc.cores.uart import UARTWishboneBridge
from litescope import LiteScopeIO, LiteScopeAnalyzer