diff --git a/litescope/core/port.py b/litescope/core/port.py
index e7c8ee7..d606938 100644
--- a/litescope/core/port.py
+++ b/litescope/core/port.py
@@ -78,7 +78,7 @@ class LiteScopeEdgeDetectorUnit(Module):
         # # #
 
         self.submodules.buffer = Buffer(self.sink.description)
-        self.comb += Record.connect(self.sink, self.buffer.d)
+        self.comb += self.sink.connect(self.buffer.d)
 
         rising = Signal(dw)
         self.comb += rising.eq(self.rising_mask & sink.data & ~self.buffer.q.data)
diff --git a/litescope/core/storage.py b/litescope/core/storage.py
index ba2f61e..cfb2051 100644
--- a/litescope/core/storage.py
+++ b/litescope/core/storage.py
@@ -23,7 +23,7 @@ class LiteScopeSubSamplerUnit(Module):
         done = Signal()
         self.comb += [
             done.eq(self.counter >= self.value),
-            Record.connect(sink, source),
+            sink.connect(source),
             source.stb.eq(sink.stb & done),
             self.counter_ce.eq(source.ack),
             self.counter_reset.eq(source.stb & source.ack & done)
@@ -53,7 +53,7 @@ class LiteScopeRunLengthEncoderUnit(Module):
         # # #
 
         self.submodules.buf = buf = Buffer(sink.description)
-        self.comb += Record.connect(sink, buf.d)
+        self.comb += sink.connect(buf.sink)
 
         counter = Signals(max=length)
         counter_reset = Signal()
@@ -70,12 +70,12 @@ class LiteScopeRunLengthEncoderUnit(Module):
         change = Signal()
         self.comb += change.eq(
             sink.stb &
-            (sink.data != buf.q.data)
+            (sink.data != buf.source.data)
         )
 
         self.submodules.fsm = fsm = FSM(reset_state="BYPASS")
         fsm.act("BYPASS",
-            Record.connect(buf.q, source),
+            buf.source.connect(source),
             counter_reset.eq(1),
             If(sink.stb & ~change,
                 If(self.enable,
@@ -84,7 +84,7 @@ class LiteScopeRunLengthEncoderUnit(Module):
             )
         )
         fsm.act("COUNT",
-            buf.q.ack.eq(1),
+            buf.source.ack.eq(1),
             counter_ce.eq(sink.stb),
             If(~self.enable,
                 NextState("BYPASS")
@@ -92,7 +92,7 @@ class LiteScopeRunLengthEncoderUnit(Module):
                 source.stb.eq(1),
                 source.data[:len(counter)].eq(counter),
                 source.data[-1].eq(1),  # Set RLE bit
-                buf.q.ack.eq(source.ack),
+                buf.source.ack.eq(source.ack),
                 If(source.ack,
                     NextState("BYPASS")
                 )
diff --git a/litescope/core/trigger.py b/litescope/core/trigger.py
index 6c2b7a5..f2bac00 100644
--- a/litescope/core/trigger.py
+++ b/litescope/core/trigger.py
@@ -75,6 +75,6 @@ class LiteScopeTrigger(Module, AutoCSR):
                 port.sink.stb.eq(self.sink.stb),
                 port.sink.data.eq(self.sink.data),
                 self.sink.ack.eq(1),
-                Record.connect(port.source, self.sum.sinks[i])
+                port.source.connect(self.sum.sinks[i])
             ]
-        self.comb += Record.connect(self.sum.source, self.source)
+        self.comb += self.sum.source.connect(self.source)
diff --git a/litescope/frontend/logic_analyzer.py b/litescope/frontend/logic_analyzer.py
index 057502e..56164fd 100644
--- a/litescope/frontend/logic_analyzer.py
+++ b/litescope/frontend/logic_analyzer.py
@@ -41,8 +41,8 @@ class LiteScopeLogicAnalyzer(Module, AutoCSR):
                 self.submodules += RenameClockDomains(input_buffer, clk_domain)
             else:
                 self.submodules += input_buffer
-            self.comb += Record.connect(sink, intput_buffer.d)
-            sink = intput_buffer.q
+            self.comb += sink.connect(intput_buffer.sink)
+            sink = intput_buffer.source
 
         # clock domain crossing (optional, required when capture_clk is not sys_clk)
         # XXX : sys_clk must be faster than capture_clk, add Converter on data to remove this limitation
@@ -50,7 +50,7 @@ class LiteScopeLogicAnalyzer(Module, AutoCSR):
             self.submodules.fifo = AsyncFIFO(self.sink.description, 32)
             self.submodules += RenameClockDomains(self.fifo,
                 {"write": self.clk_domain, "read": "sys"})
-            self.comb += Record.connect(sink, self.fifo.sink)
+            self.comb += sink.connect(self.fifo.sink)
             sink = self.fifo.source
 
         # connect trigger
@@ -62,23 +62,23 @@ class LiteScopeLogicAnalyzer(Module, AutoCSR):
         # insert subsampler (optional)
         if self.with_subsampler:
             self.submodules.subsampler = LiteScopeSubSampler(self.dw)
-            self.comb += Record.connect(sink, self.subsampler.sink)
+            self.comb += sink.connect(self.subsampler.sink)
             sink = self.subsampler.source
 
         # connect recorder
-        self.comb += Record.connect(self.trigger.source, self.recorder.trigger_sink)
+        self.comb += self.trigger.source.connect(self.recorder.trigger_sink)
         if self.with_rle:
             self.submodules.rle = LiteScopeRunLengthEncoder(self.dw, self.rle_length)
             self.comb += [
-                Record.connect(sink, self.rle.sink),
-                Record.connect(self.rle.source, self.recorder.data_sink),
+                sink.connect(self.rle.sink),
+                self.rle.source.connect(self.recorder.data_sink),
                 self.rle.external_enable.eq(self.recorder.post_hit)
             ]
         else:
             self.submodules.delay_buffer = Buffer(self.sink.description)
             self.comb += [
-                Record.connect(sink, self.delay_buffer.d),
-                Record.connect(self.delay_buffer.q, self.recorder.data_sink)
+                sink.connect(self.delay_buffer.sink),
+                self.delay_buffer.source.connect(self.recorder.data_sink)
             ]
 
     def export(self, vns, filename):