From 577d83dc80107e940cd81d12d5982444db0fc249 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 17 Nov 2015 00:23:51 +0100
Subject: [PATCH] test: use new RemoteClient/RemoveServer provided by LiteX

---
 example_designs/test/Makefile               | 19 ---------
 example_designs/test/make.py                | 30 --------------
 example_designs/test/test_inout.py          | 23 ++++++-----
 example_designs/test/test_logic_analyzer.py | 45 +++++++++++----------
 example_designs/test/test_regs.py           | 25 +++++++-----
 5 files changed, 54 insertions(+), 88 deletions(-)
 delete mode 100644 example_designs/test/Makefile
 delete mode 100644 example_designs/test/make.py

diff --git a/example_designs/test/Makefile b/example_designs/test/Makefile
deleted file mode 100644
index e5b2551..0000000
--- a/example_designs/test/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
-COREDIR = ../../
-PYTHON = python3
-SERIAL ?= 2
-
-CMD = PYTHONPATH=$(COREDIR) $(PYTHON) make.py --port $(SERIAL)
-
-test_regs:
-	$(CMD) test_regs
-
-test_inout:
-	$(CMD) test_inout
-
-test_logic_analyzer:
-	$(CMD) test_logic_analyzer
-
-all: test_regs test_inout test_logic_analyzer
-
-clean:
-	rm -f *.csv dump.*
diff --git a/example_designs/test/make.py b/example_designs/test/make.py
deleted file mode 100644
index 99f1093..0000000
--- a/example_designs/test/make.py
+++ /dev/null
@@ -1,30 +0,0 @@
-#!/usr/bin/env python3
-import argparse
-import importlib
-
-
-def _get_args():
-    parser = argparse.ArgumentParser()
-    parser.add_argument("-b", "--bridge", default="uart", help="Bridge to use")
-    parser.add_argument("--port", default="2", help="UART port")
-    parser.add_argument("--baudrate", default=115200, help="UART baudrate")
-    parser.add_argument("--busword", default=32, help="CSR busword")
-
-    parser.add_argument("test", nargs="+", help="specify a test")
-
-    return parser.parse_args()
-
-if __name__ == "__main__":
-    args = _get_args()
-    if args.bridge == "uart":
-        from misoclib.com.uart.software.wishbone import UARTWishboneBridgeDriver
-        port = args.port if not args.port.isdigit() else int(args.port)
-        wb = UARTWishboneBridgeDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
-        ValueError("Invalid bridge {}".format(args.bridge))
-
-    def _import(name):
-        return importlib.import_module(name)
-
-    for test in args.test:
-        t = _import(test)
-        t.main(wb)
diff --git a/example_designs/test/test_inout.py b/example_designs/test/test_inout.py
index 115e7ba..d6cde7b 100644
--- a/example_designs/test/test_inout.py
+++ b/example_designs/test/test_inout.py
@@ -1,4 +1,5 @@
 import time
+from litex.soc.tools.remote import RemoteClient
 from litescope.software.driver.inout import LiteScopeInOutDriver
 
 
@@ -25,13 +26,17 @@ def led_anim1(inout):
             time.sleep(i*i*0.0020)
             led_data = (led_data >> 1)
 
+wb = RemoteClient()
+wb.open()
 
-def main(wb):
-    inout = LiteScopeInOutDriver(wb.regs, "inout")
-    wb.open()
-    # # #
-    led_anim0(inout)
-    led_anim1(inout)
-    print("{:02X}".format(inout.read()))
-    # # #
-    wb.close()
+# # #
+
+inout = LiteScopeInOutDriver(wb.regs, "inout")
+
+led_anim0(inout)
+led_anim1(inout)
+print("{:02X}".format(inout.read()))
+
+# # #
+
+wb.close()
diff --git a/example_designs/test/test_logic_analyzer.py b/example_designs/test/test_logic_analyzer.py
index 4112d47..889f148 100644
--- a/example_designs/test/test_logic_analyzer.py
+++ b/example_designs/test/test_logic_analyzer.py
@@ -1,26 +1,29 @@
-from litescope.software.driver.logic_analyzer import LiteScopeLogicAnalyzerDriver
+from litex.soc.tools.remote import RemoteClient
 
+wb = RemoteClient()
+wb.open()
 
-def main(wb):
-    wb.open()
-    # # #
-    logic_analyzer = LiteScopeLogicAnalyzerDriver(wb.regs, "logic_analyzer", debug=True)
+# # #
 
-    cond = {} # immediate trigger
-    logic_analyzer.configure_term(port=0, cond=cond)
-    logic_analyzer.configure_sum("term")
-    logic_analyzer.configure_subsampler(1)
-    # logic_analyzer.configure_qualifier(1)
-    logic_analyzer.configure_rle(1)
-    logic_analyzer.run(offset=128, length=256)
+logic_analyzer = LiteScopeLogicAnalyzerDriver(wb.regs, "logic_analyzer", debug=True)
 
-    while not logic_analyzer.done():
-        pass
-    logic_analyzer.upload()
+cond = {} # immediate trigger
+logic_analyzer.configure_term(port=0, cond=cond)
+logic_analyzer.configure_sum("term")
+logic_analyzer.configure_subsampler(1)
+# logic_analyzer.configure_qualifier(1)
+logic_analyzer.configure_rle(1)
+logic_analyzer.run(offset=128, length=256)
 
-    logic_analyzer.save("dump.vcd")
-    logic_analyzer.save("dump.csv")
-    logic_analyzer.save("dump.py")
-    logic_analyzer.save("dump.sr")
-    # # #
-    wb.close()
+while not logic_analyzer.done():
+    pass
+logic_analyzer.upload()
+
+logic_analyzer.save("dump.vcd")
+logic_analyzer.save("dump.csv")
+logic_analyzer.save("dump.py")
+logic_analyzer.save("dump.sr")
+
+# # #
+
+wb.close()
diff --git a/example_designs/test/test_regs.py b/example_designs/test/test_regs.py
index 21deed9..822a232 100644
--- a/example_designs/test/test_regs.py
+++ b/example_designs/test/test_regs.py
@@ -1,9 +1,16 @@
-def main(wb):
-    wb.open()
-    regs = wb.regs
-    # # #
-    print("sysid     : 0x{:04x}".format(regs.identifier_sysid.read()))
-    print("revision  : 0x{:04x}".format(regs.identifier_revision.read()))
-    print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
-    # # #
-    wb.close()
+from litex.soc.tools.remote import RemoteClient
+
+wb = RemoteClient()
+wb.open()
+
+# # #
+
+identifier = ""
+for i in range(30):
+    identifier += chr(wb.read(wb.bases.identifier_mem + 4*(i+1))) # TODO: why + 1?
+print(identifier)
+print("frequency : {}MHz".format(wb.constants.system_clock_frequency/1000000))
+
+# # #
+
+wb.close()